reboot related questions

[Jason Chen]

hi,all,
I built up a system which based on MPC8248,32M NOR flash,128M SDRAM.I set the HRCW to boot from 0x0 address(CIP = 0 & BMS=1);and BR0 = 0xfe00xxxx for flash(base addr = 0xfe000000,my u-boot was burned from 0xfe000000);BR2 = 0x000000xx for sdram(base addr = 0x00).
it's Ok,the u-boot and kernel all run successfully; but I met a problem -- reboot cmd failed.After some effort, I found it can run successfully by modify /linux/arch/ppc/kernel/head.S m8260_gorom function below:

    .globl  m8260_gorom /* r4 = addr in the rom */
m8260_gorom:
	mfmsr	r0
	rlwinm	r0,r0,0,17,15	/* clear MSR_EE in r0 */
	sync
	mtmsr	r0
	sync
	mfspr	r11, HID0
	lis	r10, 0
	ori	r10,r10,HID0_ICE|HID0_DCE
	andc	r11, r11, r10
	mtspr	HID0, r11
	isync
	li	r5, MSR_
	lis	r6,2f at h
	addis	r6,r6,-KERNELBASE at h
	ori	r6,r6,2f at l
	mtspr	SRR0,r6
	mtspr	SRR1,r5
	isync
	sync
	rfi
2:
	mtlr	r4
	blr
                                  
In these codes, MSR_ equal MSR_ME|MSR_RI originally,after be set to MSR_ME|MSR_RI|MSR_IP,the reboot can run successfully.
My questions come out:
1) You know,the bit MSR_IP represent that exceptions are vectored to the physical address 0xFFFn_nnnn(IP = 1) or 0x000n_nnnn(IP = 0);but in my system,the real exception vector was set to 0xfe00_0x00,so how CPU could find them in 0xFFFn_nnnn ??
2) why m8260_gorom has to used a rfi instruction? why not just to set the MSR to appropriate value and move PC to rom?
3) there are not interrupts happened in u-boot? Because in my system,after reset,the BR0 soon be changed to 0xfe00xxxx,at the same time,MSR[ip] = 0 (HRCW show this),the vector will be in the sdram(0x000n_nnnn) where are not initiated,so while u-boot running,there are not interrupts happened? am i right?
4) assuming 3) was right, then why the m8260_gorom function above has to set the MSR_ to MSR_ME|MSR_RI|MSR_IP? Because no interrupts,where are the vectors seems not important?

It's boring...

Jason