[OpenPower-Firmware] [EXTERNAL] Re: Hardware documentation

[Daniel M Crowell]

The SBE determines the logical memory address that the bootloader gets
loaded into, that is the HRMOR.  There are some explicit operations done to
preload these addresses into the cache at the expected address.  Depending
on your box and code level, Hostboot starts at 128MB or 4GB-256MB.  The
bootloader actually runs at +2MB from where Hostboot eventually gets
started at, so you end up with this:
	128 MB = Hostboot
	129 MB = HBB with ECC (pulled from PNOR)
	130 MB = Bootloader
	131 MB = HBB without ECC (used for secureboot verification)
Note that HRMOR=130M during bootloader and it switches to 128M for
Hostboot.

> In coreboot terminology bootblock and romstage will run out of the cache,
and romstage will init the ram enough to load ramstage into it.
We don't really divide between cache and cache+memory with regards to our
code load.  Our division is based on code being pageable (HBI) versus not
(HBB).  We require a lot of code from HBI to get mainstore memory online.

--
Dan Crowell
Senior Software Engineer - Power Systems Enablement Firmware
IBM Rochester: t/l 553-2987
dcrowell at us.ibm.com



From:	"Marty E. Plummer" <hanetzer at startmail.com>
To:	Andrew Donnellan <ajd at linux.ibm.com>
Cc:	Daniel M Crowell <dcrowell at us.ibm.com>,
            openpower-firmware at lists.ozlabs.org
Date:	10/26/2019 07:50 AM
Subject:	[EXTERNAL] Re: [OpenPower-Firmware] Hardware documentation



On Thu, Oct 17, 2019 at 06:16:24PM +1100, Andrew Donnellan wrote:
> On 15/10/19 9:55 am, Marty E. Plummer wrote:
> > > On Mon, Oct 14, 2019 at 01:34:07AM +0000, Daniel M Crowell wrote:
> > > > think a goodly portion of it is directly executed (but I seem to
recall
> > > > reading that some of it just calls to the bits of hostboot still in
> > > > memory after it gets loaded, pinged Stewart Smith about that).
> > > There isn't anything in skiboot that requires any hostboot logic to
be resident.
> > Maybe I'm thinking of the linux kernel drivers then.
>
> Yep, you're thinking of the PRD diagnostics which call into HBRT
(HostBoot
> RunTime). You can do without it though.
>
Ah yep, that was it.

On another note, address spaces. In coreboot terminology bootblock and
romstage will run out of the cache, and romstage will init the ram
enough to load ramstage into it. One thing I'm wondering about is the
layout of memory in these stages (analogous to hbibl and hbicore or so).

Does it start at 0x0 or some other location? (both cache for early boot
and 'normal' dram)
>
> --
> Andrew Donnellan              OzLabs, ADL Canberra
> ajd at linux.ibm.com             IBM Australia Limited
>



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