<html><body><p><font size="2">The SBE determines the logical memory address that the bootloader gets loaded into, that is the HRMOR. There are some explicit operations done to preload these addresses into the cache at the expected address. Depending on your box and code level, Hostboot starts at 128MB or 4GB-256MB. The bootloader actually runs at +2MB from where Hostboot eventually gets started at, so you end up with this:</font><br><font size="2"> 128 MB = Hostboot</font><br><font size="2"> 129 MB = HBB with ECC (pulled from PNOR)</font><br><font size="2"> 130 MB = Bootloader</font><br><font size="2"> 131 MB = HBB without ECC (used for secureboot verification)</font><br><font size="2">Note that HRMOR=130M during bootloader and it switches to 128M for Hostboot.</font><br><br><tt><font size="2">> In coreboot terminology bootblock and romstage will run out of the cache, and romstage will init the ram enough to load ramstage into it. </font></tt><br><font size="2">We don't really divide between cache and cache+memory with regards to our code load. Our division is based on code being pageable (HBI) versus not (HBB). We require a lot of code from HBI to get mainstore memory online.</font><br><font size="2"><br>--<br>Dan Crowell<br>Senior Software Engineer - Power Systems Enablement Firmware<br>IBM Rochester: t/l 553-2987<br>dcrowell@us.ibm.com</font><br><br><img width="16" height="16" src="cid:1__=09BB0E31DFC3DE658f9e8a93df938690918c09B@" border="0" alt="Inactive hide details for "Marty E. Plummer" ---10/26/2019 07:50:56 AM---On Thu, Oct 17, 2019 at 06:16:24PM +1100, Andrew Donne"><font size="2" color="#424282">"Marty E. Plummer" ---10/26/2019 07:50:56 AM---On Thu, Oct 17, 2019 at 06:16:24PM +1100, Andrew Donnellan wrote: > On 15/10/19 9:55 am, Marty E. Pl</font><br><br><font size="2" color="#5F5F5F">From: </font><font size="2">"Marty E. Plummer" <hanetzer@startmail.com></font><br><font size="2" color="#5F5F5F">To: </font><font size="2">Andrew Donnellan <ajd@linux.ibm.com></font><br><font size="2" color="#5F5F5F">Cc: </font><font size="2">Daniel M Crowell <dcrowell@us.ibm.com>, openpower-firmware@lists.ozlabs.org</font><br><font size="2" color="#5F5F5F">Date: </font><font size="2">10/26/2019 07:50 AM</font><br><font size="2" color="#5F5F5F">Subject: </font><font size="2">[EXTERNAL] Re: [OpenPower-Firmware] Hardware documentation</font><br><hr width="100%" size="2" align="left" noshade style="color:#8091A5; "><br><br><br><tt><font size="2">On Thu, Oct 17, 2019 at 06:16:24PM +1100, Andrew Donnellan wrote:<br>> On 15/10/19 9:55 am, Marty E. Plummer wrote:<br>> > > On Mon, Oct 14, 2019 at 01:34:07AM +0000, Daniel M Crowell wrote:<br>> > > > think a goodly portion of it is directly executed (but I seem to recall<br>> > > > reading that some of it just calls to the bits of hostboot still in<br>> > > > memory after it gets loaded, pinged Stewart Smith about that).<br>> > > There isn't anything in skiboot that requires any hostboot logic to be resident.<br>> > Maybe I'm thinking of the linux kernel drivers then.<br>> <br>> Yep, you're thinking of the PRD diagnostics which call into HBRT (HostBoot<br>> RunTime). You can do without it though.<br>> <br>Ah yep, that was it.<br><br>On another note, address spaces. In coreboot terminology bootblock and<br>romstage will run out of the cache, and romstage will init the ram<br>enough to load ramstage into it. One thing I'm wondering about is the<br>layout of memory in these stages (analogous to hbibl and hbicore or so).<br><br>Does it start at 0x0 or some other location? (both cache for early boot<br>and 'normal' dram)<br>> <br>> -- <br>> Andrew Donnellan OzLabs, ADL Canberra<br>> ajd@linux.ibm.com IBM Australia Limited<br>> <br><br></font></tt><br><br><BR>
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