[Skiboot] LPC bus regs question

[Marty E. Plummer]

On Mon, Oct 19, 2020 at 11:48:44AM +1100, Oliver O'Halloran wrote:
> On Fri, Oct 16, 2020 at 4:23 AM Marty E. Plummer <hanetzer at startmail.com> wrote:
> These are the offsets to the register blocks of the LPC controller and
> OPB bus controller. I *think* those registers are documented in the
> OPB and LPC specs. The internal docs call out the following as
> reference material:
> 
Not seeing the opb-master, opb-arbiter, and lpc-controller regs in these
docs (available on google)
> • On-Chip Peripheral Bus (OPB) Architecture Specifications, Version
> 2.1, SA-14-2528-02, April 2001.
> • 32-Bit OPB Arbiter Core Data Book, Revision 1, SA15-5821-01, March 9, 2007.
> • LPC HOST Controller Specification, Version 1.1, May 26, 2009.
> • Intel Low Pin Count (LPC) Interface Specification, Revision 1.1, August 2002.
> • Serialized IRQ Support for PCI System Specification, Revision 6.0
> 
> Personally I'd just go off what skiboot / hostboot / the SBE are doing
> and ignore the actual specs. They're pretty dry.
> 
Yeah, I just don't like to cargo-cult code around without at least semi
understanding it. On that note, lpc_{in,out}{b,w,l} in include/lpc.h
seem to indicate that these accesses are little endian, whereas
lpc_fw_{read,write}32 are big endian according to the comments, but
there is no be/le byteswapping going on for them? Is that because for
the moment skiboot is only big or little endian so no swapping is needed?
> > On another note, does the lpc controller appear at a particular address
> > from the host's perspective, aside from the 0x603xx address set by scom
> > 0x90040?
> 
> I don't think so. On P8 you needed to use a PIO-style xscom interface
> to access the OPB, but that was replaced with the MMIO bridge on P9.
> The LPC master is intended to be self-initialising so there's not much
> you need to do to it beyond setting up the MMIO BAR.
>

On another note, given this snippet of dts:
```
ipmi-bt at ie4 {
	...
	reg = <0x01 0xe4 0x03>
	...
};
mbox at i1000 {
	...
	reg = <0x01 0x1000 0x06>
	...
};
serial at i3f8 {
	...
	reg = <0x01 0x3f8 0x01>
	...
};
```
I can easily determine the first cell as indicating its in the io region,
the second sell is the offset within it, but what's the third cell? And
are these considered pnp devices in the sense they are on x86 platforms?
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