[Skiboot] LPC bus regs question

[Oliver O'Halloran]

On Fri, Oct 16, 2020 at 4:23 AM Marty E. Plummer <hanetzer at startmail.com> wrote:
>
> So, in hw/lpc.c, lines 160-164 a number of addresses are defined.
> As I'm working on a lpc driver for p9 in coreboot, and I'm not
> finding any particular docs on why these are what they are. Is this
> defined host-side or bmc-side? If I'm missing something obvious in
> the public docs or skiboot/hostboot source code I'd appreciate a
> heads up on it.

The full chain from core to the BMC for the LPC bus is something like this:

Host CPU <-> PowerBus <-> OPB <-> LPC <-> BMC

The On-Chip Peripheral bus (OPB) is an old bus that was used to attach
random peripherals to the CPU on IBM embedded SoCs. We still use it
for random bits and pieces including the LPC interface. Each LPC
address space is accessible via memory mapped range on the OPB. So on
the host side the LPC driver does an MMIO into the OPB address space
and eventually that'll be translated into the correct type of LPC
cycle. From hw/lpc.c:160:

 160 static uint32_t lpc_io_opb_base         = 0xd0010000;
 161 static uint32_t lpc_mem_opb_base        = 0xe0000000;
 162 static uint32_t lpc_fw_opb_base         = 0xf0000000;

These are the base addresses within the OPB bus address space for the
LPC IO/MEM/FW address spaces. These can be configured by a register in
the LPC master, but we never do. The addresses above are the defaults
set by the HW after a reset.

 163 static uint32_t lpc_reg_opb_base        = 0xc0012000;
 164 static uint32_t opb_master_reg_base     = 0xc0010000;

These are the offsets to the register blocks of the LPC controller and
OPB bus controller. I *think* those registers are documented in the
OPB and LPC specs. The internal docs call out the following as
reference material:

• On-Chip Peripheral Bus (OPB) Architecture Specifications, Version
2.1, SA-14-2528-02, April 2001.
• 32-Bit OPB Arbiter Core Data Book, Revision 1, SA15-5821-01, March 9, 2007.
• LPC HOST Controller Specification, Version 1.1, May 26, 2009.
• Intel Low Pin Count (LPC) Interface Specification, Revision 1.1, August 2002.
• Serialized IRQ Support for PCI System Specification, Revision 6.0

Personally I'd just go off what skiboot / hostboot / the SBE are doing
and ignore the actual specs. They're pretty dry.

> On another note, does the lpc controller appear at a particular address
> from the host's perspective, aside from the 0x603xx address set by scom
> 0x90040?

I don't think so. On P8 you needed to use a PIO-style xscom interface
to access the OPB, but that was replaced with the MMIO bridge on P9.
The LPC master is intended to be self-initialising so there's not much
you need to do to it beyond setting up the MMIO BAR.

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