[Skiboot] [PATCH] phb4: Minor CAPP init cleanup

[Michael Neuling]

On Mon, 2018-04-23 at 11:08 +0200, christophe lombard wrote:
> Le 23/04/2018 à 07:41, Michael Neuling a écrit :
> > Currently we RMW the TRANSPORT_CONTROL register and then RMW it again
> > for no good reason. Make this a single RMW.
> > 
> > Signed-off-by: Michael Neuling <mikey at neuling.org>
> > ---
> >   hw/phb4.c | 3 ---
> >   1 file changed, 3 deletions(-)
> > 
> > diff --git a/hw/phb4.c b/hw/phb4.c
> > index 50e1be1c4c..134d1747b5 100644
> > --- a/hw/phb4.c
> > +++ b/hw/phb4.c
> > @@ -3756,10 +3756,7 @@ static void phb4_init_capp_regs(struct phb4 *p,
> > uint32_t capp_eng)
> >   			reg |= PPC_BIT(60);
> >   		}
> >   	}
> > -	xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);
> > -
> >   	/* Initialize CI Store Buffers */
> > -	xscom_read(p->chip_id, TRANSPORT_CONTROL + offset, &reg);
> >   	reg |= PPC_BIT(63);
> >   	xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);
> > 
> 
> Hi Mikey
> 
> As Nicholas Ollerich pointed out during the bringup of capi2, the 
> transport control register needs to be loaded in two steps.
> Once the register values have been set, we have to write bit 63 to a 
> '1', which loads the register values into the ci store buffer logic.
> Bit 63 always reads back as a zero but to load the ci store buffer 
> values in capp the transition of 0 to 1 of bit 63 must be seen.

Arrh, can you add a comment to that effect in the code?  Otherwise it looks
wrong.

Mikey