[Skiboot] [PATCH] NX: Add NX coprocessor init opal call

[Haren Myneni]

The read offset (4:11) in Receive FIFO control register is incremented
by FIFO size whenever CRB read by NX. But the index in RxFIFO has to
match with the corresponding entry in FIFO maintained by VAS in kernel.
VAS entry is reset to 0 with opening the receive window during driver
initialization. So when NX842 is reloaded, possibility of mismatch
between RxFIFO control register and VAS entries in kernel. It might
cause CRB failure / timeout from NX.
    
This patch adds nx_coproc_init opal call for kernel to initialize
readOffset (4:11) and Queued (15:23) in RxFIFO control register.
    
Signed-off-by: Haren Myneni <haren at us.ibm.com>

diff --git a/hw/nx-compress.c b/hw/nx-compress.c
index 9b89664..cf1c3e9 100644
--- a/hw/nx-compress.c
+++ b/hw/nx-compress.c
@@ -21,6 +21,7 @@
 #include <cpu.h>
 #include <nx.h>
 #include <vas.h>
+#include <opal.h>
 
 static int nx_cfg_umac_tx_wc(u32 gcid, u64 xcfg)
 {
@@ -206,14 +207,75 @@ int nx_cfg_rx_fifo(struct dt_node *node, const char *compat,
 	return 0;
 }
 
+static int nx_init_fifo_ctrl(u32 gcid, u64 fifo_ctrl)
+{
+	u64 cfg;
+	int rc = 0;
+
+	rc = xscom_read(gcid, fifo_ctrl, &cfg);
+	if (rc)
+		return rc;
+
+	cfg = SETFIELD(NX_P9_RX_FIFO_CTRL_READ_OFFSET, cfg, 0);
+	cfg = SETFIELD(NX_P9_RX_FIFO_CTRL_QUEUED, cfg, 0);
+
+	rc = xscom_write(gcid, fifo_ctrl, cfg);
+
+	return rc;
+}
+
+
+static int opal_nx_coproc_init(u32 gcid, u32 ct)
+{
+	struct proc_chip *chip;
+	u64 fifo, fifo_hi;
+	u32 nx_base;
+	int rc;
+
+	chip =  get_chip(gcid);
+	if (!chip)
+		return OPAL_PARAMETER;
+
+	nx_base =  chip->nx_base;
+	if (!nx_base)
+		return OPAL_PARAMETER;
+
+	switch (ct) {
+	case NX_CT_842:
+		fifo_hi = nx_base + NX_P9_842_HIGH_PRI_RX_FIFO_CTRL;
+		fifo = nx_base + NX_P9_842_NORMAL_PRI_RX_FIFO_CTRL;
+		break;
+	case NX_CT_GZIP:
+		fifo_hi = nx_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_CTRL;
+		fifo = nx_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_CTRL;
+		break;
+	default:
+		prlog(PR_EMERG, "OPAL: Unknown NX coprocessor type\n");
+		return OPAL_PARAMETER;
+	}
+
+	rc  = nx_init_fifo_ctrl(gcid, fifo_hi);
+
+	if (!rc)
+		rc  = nx_init_fifo_ctrl(gcid, fifo);
+
+	return rc;
+}
+
+opal_call(OPAL_NX_COPROC_INIT, opal_nx_coproc_init, 2);
+
 void nx_create_compress_node(struct dt_node *node)
 {
 	u32 gcid, pb_base;
+	struct proc_chip *chip;
 	int rc;
 
 	gcid = dt_get_chip_id(node);
 	pb_base = dt_get_address(node, 0, NULL);
 
+	chip = get_chip(gcid);
+	chip->nx_base =  pb_base;
+
 	prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base);
 
 	if (dt_node_is_compatible(node, "ibm,power9-nx")) {
diff --git a/include/chip.h b/include/chip.h
index 43b5ea5..81e435c 100644
--- a/include/chip.h
+++ b/include/chip.h
@@ -216,6 +216,8 @@ struct proc_chip {
 
 	struct vas		*vas;
 
+	/* Used by hw/nx-compress.c */
+	uint64_t		nx_base;
 	/* location code of this chip */
 	const uint8_t		*loc_code;
 };
diff --git a/include/nx.h b/include/nx.h
index c2f7dfc..0322349 100644
--- a/include/nx.h
+++ b/include/nx.h
@@ -149,6 +149,7 @@
 #define NX_P9_GZIP_HIGH_PRI_RX_FIFO_CTRL	NX_P9_SAT(0x3, 0x05)
 #define NX_P9_842_NORMAL_PRI_RX_FIFO_CTRL	NX_P9_SAT(0x3, 0x0c)
 #define NX_P9_GZIP_NORMAL_PRI_RX_FIFO_CTRL	NX_P9_SAT(0x3, 0x0e)
+#define	  NX_P9_RX_FIFO_CTRL_READ_OFFSET		PPC_BITMASK(4, 11)
 #define   NX_P9_RX_FIFO_CTRL_QUEUED			PPC_BITMASK(15, 23)
 #define   NX_P9_RX_FIFO_CTRL_HPRI_MAX_READ		PPC_BITMASK(27, 35)
 
diff --git a/include/opal-api.h b/include/opal-api.h
index df71cf2..deb2b49 100644
--- a/include/opal-api.h
+++ b/include/opal-api.h
@@ -223,7 +223,8 @@
 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR		164
 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR		165
 #define OPAL_HANDLE_HMI2			166
-#define OPAL_LAST				166
+#define OPAL_NX_COPROC_INIT			167
+#define OPAL_LAST				167
 
 #define QUIESCE_HOLD			1 /* Spin all calls at entry */
 #define QUIESCE_REJECT			2 /* Fail all calls with OPAL_BUSY */