[Skiboot] [PATCH] mambo/mambo_utils.tcl: Inject an MCE at a specified address
Balbir Singh
bsingharora at gmail.com
Wed Apr 11 07:00:06 AEST 2018
On Tue, Apr 10, 2018 at 11:14 PM, Nicholas Piggin <npiggin at gmail.com> wrote:
> On Tue, 10 Apr 2018 21:25:18 +1000
> Balbir Singh <bsingharora at gmail.com> wrote:
>
>> Currently we don't support injecting an MCE on a specific address.
>> This is useful for testing functionality like memcpy_mcsafe()
>> (see https://patchwork.ozlabs.org/cover/893339/)
>>
>> This patch refactors exc_mce into setup_mce and exc_mce. setup_mce
>> is generally useful to setup a MCE context with variables DSISR,
>> SRR1 and DAR. setup_mce supports setting up dsisr as a new
>> function argument. It's useful when we want to set up both the
>> cause and DSIR.
>
> Hum, I actually have a patch sitting around that reworks this stuff
> quite significantly for stop states (which mambo doesn't handle very
> well). It doesn't look like there's a big conflict, but if I can send
> it and get you to test and merge on top of it that would be good.
Sure, send it across
>
>>
>> The core of the functionality is a routine called
>> inject_mce_ue_on_addr, which takes an addr argument and injects
>> an MCE (load/store with UE) when the specified address is accessed
>> by code. This functionality can easily be enhanced to cover
>> instruction UE's as well.
>>
>> Signed-off-by: Balbir Singh <bsingharora at gmail.com>
>> ---
>> external/mambo/mambo_utils.tcl | 29 ++++++++++++++++++++++++-----
>> 1 file changed, 24 insertions(+), 5 deletions(-)
>>
>> diff --git a/external/mambo/mambo_utils.tcl b/external/mambo/mambo_utils.tcl
>> index 7a27f0f4..a9225e3e 100644
>> --- a/external/mambo/mambo_utils.tcl
>> +++ b/external/mambo/mambo_utils.tcl
>> @@ -442,11 +442,12 @@ proc mce_trigger { args } {
>> #
>> # Default with no arguments is a recoverable i-side TLB multi-hit
>> # Other options:
>> -# d_side=1 cause=0x80 - recoverable d-side SLB multi-hit
>> +# d_side=1 dsisr=0x80 - recoverable d-side SLB multi-hit
>> +# d_side=1 dsisr=0x8000, cause=0x1 - ue error on instruction fetch
>> # d_side=0 cause=0xd - unrecoverable i-side async store timeout (POWER9 only)
>> # d_side=0 cause=0x1 - unrecoverable i-side ifetch
>> #
>> -proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 } } {
>> +proc setup_mce { { d_side 0 } {dsisr 0x5} { cause 0x5 } { recoverable 1 }} {
>> variable SRR1
>> variable DSISR
>> variable DAR
>> @@ -466,11 +467,10 @@ proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 } } {
>> set msr_ri 0x0
>> }
>>
>> - # recoverable d-side SLB multihit
>> if { $d_side } {
>> set is_dside 1
>> - set SRR1_mc_cause 0x0
>> - set DSISR $cause
>> + set SRR1_mc_cause $cause
>> + set DSISR $dsisr
>> set DAR 0xdeadbeefdeadbeef
>> } else {
>> set is_dside 0
>
> This doesn't seem right. ue error on ifetch is i-side which can not
> set DSISR. I have the ifetch UE in the comment. What was wrong with
> the original code here?
>
This is called from a trigger on data access and sets up an MCE with
d_side set to 1.
So it's not an ifetch i-side change. Am I missing something?
Balbir Singh
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