[Skiboot] [PATCH 2/3] phb4: Enable the PCIe slotcap on pluggable slots

[Oliver O'Halloran]

Enables reporting of slot status information, etc in the config space of
the root complex. Currently this is only used to set the slot power
limit in our generic PCI code, but we might use it for other things
later on.

Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
---
 hw/phb4.c           | 20 ++++++++++++++++++++
 include/phb4-regs.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/hw/phb4.c b/hw/phb4.c
index 06d2050f829b..c72f93330699 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -624,6 +624,8 @@ static int64_t phb4_get_reserved_pe_number(struct phb *phb)
 static void phb4_root_port_init(struct phb *phb, struct pci_device *dev,
 				int ecap, int aercap)
 {
+	struct phb4 *p = phb_to_phb4(phb);
+	struct pci_slot *slot = dev->slot;
 	uint16_t bdfn = dev->bdfn;
 	uint16_t val16;
 	uint32_t val32;
@@ -639,6 +641,24 @@ static void phb4_root_port_init(struct phb *phb, struct pci_device *dev,
 
 	// FIXME: check recommended init values for phb4
 
+	/*
+	 * Enable the bridge slot capability in the root port's config
+	 * space. This should probably be done *before* we start
+	 * scanning config space, but we need a pci_device struct to
+	 * exist before we do a slot lookup so *faaaaaaaaaaaaaart*
+	 */
+	if (slot && slot->pluggable && slot->power_limit) {
+		uint64_t val;
+
+		val = in_be64(p->regs + PHB_PCIE_SCR);
+		val |= PHB_PCIE_SCR_SLOT_CAP;
+		out_be64(p->regs + PHB_PCIE_SCR, val);
+
+		/* update the cached slotcap */
+		pci_cfg_read32(phb, bdfn, ecap + PCICAP_EXP_SLOTCAP,
+				&slot->slot_cap);
+	}
+
 	/* Enable SERR and parity checking */
 	pci_cfg_read16(phb, bdfn, PCI_CFG_CMD, &val16);
 	val16 |= (PCI_CFG_CMD_SERR_EN | PCI_CFG_CMD_PERR_RESP |
diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index 16a1a7405720..3f87ddcdcac8 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -267,6 +267,7 @@
 
 // FIXME add more here
 #define PHB_PCIE_SCR			0x1A00
+#define   PHB_PCIE_SCR_SLOT_CAP		PPC_BIT(15)
 #define	  PHB_PCIE_SCR_MAXLINKSPEED	PPC_BITMASK(32,35)
 
 
-- 
2.9.5