[Skiboot] [PATCH 3/9] npu2: Fix NPU/PHY0/PHY1 stack order

[Andrew Donnellan]

On 15/07/17 01:39, Reza Arbab wrote:
> As previously noted in the comments, this changed in POWER9 DD2. Add a
> stanza reverting to the old order on DD1.
>
> Cc: Alistair Popple <alistair at popple.id.au>
> Signed-off-by: Reza Arbab <arbab at linux.vnet.ibm.com>

Reviewed-by: Andrew Donnellan <andrew.donnellan at au1.ibm.com>

> ---
>  hw/npu2.c | 18 +++++++++++-------
>  1 file changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/hw/npu2.c b/hw/npu2.c
> index 2ec572d..6baeec6 100644
> --- a/hw/npu2.c
> +++ b/hw/npu2.c
> @@ -1141,18 +1141,15 @@ static void assign_mmio_bars(uint64_t gcid, uint32_t scom, uint64_t reg[2], uint
>  	uint32_t i;
>  	struct npu2_bar *bar;
>  	struct npu2_bar npu2_bars[] = {
> -		/*
> -		 * NPU_REGS must be first in this list, at least on DD1.
> -		 * On DD2, stack 0 will be used for NPU_REGS, stack 1/2 for NPU_PHY.
> -		 */
> +		/* NPU_REGS must be first in this list */

Hmm, purely for interests' sake, I should test whether this restriction 
still exists on DD2 sometime... on DD1, setting the other BARs before 
this BAR caused a checkstop.

>  		{ .type = NPU_REGS, .index = 0,
> -		  .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_PHY_BAR),
> +		  .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0, 0, NPU2_PHY_BAR),
>  		  .flags = NPU2_BAR_FLAG_ENABLED },
>  		{ .type = NPU_PHY, .index = 0,
> -		  .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0, 0, NPU2_PHY_BAR),
> +		  .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_1, 0, NPU2_PHY_BAR),
>  		  .flags = NPU2_BAR_FLAG_ENABLED },
>  		{ .type = NPU_PHY, .index = 1,
> -		  .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_1, 0, NPU2_PHY_BAR),
> +		  .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_PHY_BAR),
>  		  .flags = NPU2_BAR_FLAG_ENABLED },
>  		{ .type = NPU_NTL, .index = 0,
>  		  .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0, 0, NPU2_NTL0_BAR) },
> @@ -1174,6 +1171,13 @@ static void assign_mmio_bars(uint64_t gcid, uint32_t scom, uint64_t reg[2], uint
>  		  .reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_GENID_BAR) },
>  	};
>
> +	/* On DD1, stack 2 was used for NPU_REGS, stack 0/1 for NPU_PHY */
> +	if (is_p9dd1()) {
> +		npu2_bars[0].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_2, 0, NPU2_PHY_BAR);
> +		npu2_bars[1].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0, 0, NPU2_PHY_BAR);
> +		npu2_bars[2].reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_1, 0, NPU2_PHY_BAR);
> +	}
> +
>  	for (i = 0; i < ARRAY_SIZE(npu2_bars); i++) {
>  		bar = &npu2_bars[i];
>  		npu2_get_bar(gcid, bar);
>

-- 
Andrew Donnellan              OzLabs, ADL Canberra
andrew.donnellan at au1.ibm.com  IBM Australia Limited