[Skiboot] [PATCH] hw/npu2-hw-procedures.c: Update PHY_RESET procedure

[Alistair Popple]

Newer versions of Hostboot will have various clocks powered down by default
to save power. Therefore we need to power them up before accessing the OBUS
PHY.

Signed-off-by: Alistair Popple <alistair at popple.id.au>
---

Stewart,

Reza wants to test this before we merge it so best to wait for his
reviewed/tested-by first. Thanks!

- Alistair

hw/npu2-hw-procedures.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
index de70009..c9e7673 100644
--- a/hw/npu2-hw-procedures.c
+++ b/hw/npu2-hw-procedures.c
@@ -87,6 +87,11 @@ struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH	= {0x24e, 54, 8};
 struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH_LANE	= {0x24e, 49, 5};
 struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH_VALID= {0x24e, 48, 1};
 
+struct npu2_phy_reg NPU2_PHY_RX_CLKDIST_PDWN		= {0x204, 48, 3};
+struct npu2_phy_reg NPU2_PHY_RX_IREF_PDWN		= {0x230, 54, 1};
+struct npu2_phy_reg NPU2_PHY_TX_CLKDIST_PDWN		= {0x305, 48, 3};
+struct npu2_phy_reg NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN = {0x2e0, 60, 1};
+
 #define NPU2_PHY_REG(scom_base, reg, lane)					\
 	SETFIELD(PPC_BITMASK(27, 31), ((reg)->offset << 42) | scom_base, lane)
 
@@ -252,6 +257,12 @@ static uint32_t phy_reset(struct npu2_dev *ndev)
 {
 	int lane;
 
+	/* Power on clocks */
+	phy_write(ndev, &NPU2_PHY_RX_CLKDIST_PDWN, 0);
+	phy_write(ndev, &NPU2_PHY_RX_IREF_PDWN, 1);
+	phy_write(ndev, &NPU2_PHY_TX_CLKDIST_PDWN, 0);
+	phy_write(ndev, &NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN, 0);
+
 	FOR_EACH_LANE(ndev, lane)
 		phy_write_lane(ndev, &NPU2_PHY_RX_RUN_LANE, lane, 0);
 
-- 
2.1.4