[OpenPower-Firmware] A few questions about early hostboot

[Dean Sanner]

Hi Marty,

> I have a few additional questions about early hostboot on the power9
> platform.
>
> I know pdbg has a gdbserver which currently only works on p8 and linux
> kernel (though I may be misinterpreting the latter half). I assume the
> lack of power9 support is just some missing code for now, but I wonder
> about only supporting the linux kernel. Is there some deep-seated reason
> one could not use gbdserver on hostboot itself? It could be very useful
> for early debugging.

Stewart is correct -- there is just a different way of accessing the memory
(getmempba versus getmemproc).  I know that the IBM's SBE team had a
prototype of gdbg working against hostboot a while back.  I've copied
them on this email to see if it is still viable (there were some issues
with the virtual pages for the extended image, but if you are only
using it for early debug -- might not be an issue).

>
> Power9 processors are able to operate in both BE and LE mode, and I am
> having a bit of issue following this idea. Is there some register one
> sets to switch mode I'm missing, or does the processor just 'know' that
> 0xdeadbeef and 0xefbeadde are the same? Forgive me if this is a bad
> example but hopefully it gets my point across. In addition, is there any
> reason that hostboot couldn't be ran in either big or little endian
> (after endian specific code is fixed, obviously)?

There is nothing that prevents Hostboot from running LE mode -- just
the amount of work to port it :)

MSR bit 63 controls the LE/BE mode (where 0b0 is BE, 0b1 is LE).  If
you want to trampoline early in HB to switch you can setup the srr0/1
and then rfid to make it take effect.   You could hook it into the
following code from
https://github.com/open-power/hostboot/blob/master/src/kernel/start.S
(note that this part would need to be BE, all code after _start_postmsr
would need to be LE)

.global _start
_start:
    ;// Set thread priority high.
    or 2,2,2

    ;// Clear MSR[TA] (bit 1)
    mfmsr r2
    rldicl r2,r2,1,1    ;// Clear bit 1 - result [1-63,0]
    rotrdi r2,r2,1      ;// Rotate right 1 - result [0,63]
    ;// Set up SRR0 / SRR1 to enable new MSR.
    mtsrr1 r2
    li r2, _start_postmsr at l
    mtsrr0 r2
    lis     r9,49      ;// Want to default the NAP value
    ori     r9,r9,1    ;// Value is 0x0000000000310001
    mtspr   855,r9     ;// set actual PSSCR
    rfid


Or you can write the MSR in the SBE code where it manipulates
the starting threads architected state:
https://github.com/open-power/sbe/blob/master/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C


Dean Sanner
dsanner at us.ibm.com
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