How to configure Clock Stop Control Register

[Henbin Chang]

>
> What kernel tree are you building/booting? Can you provide a link?
> Currently we've tied the LCLK to enabling LPC2AHB bridge:
> https://github.com/openbmc/linux/blob/dev-4.13/arch/arm/boot
> /dts/aspeed-g5.dtsi#L302
> You may need to add the following to your dts if you've developed your own:
> ```
> &lpc_ctrl {
>         status = "okay";
> };


Hi Andrew,

Thanks  for your quick response.

I use dev-4.13 branch (the last commit is aca92be80c008bceeb6fb62fd1d450
b5be5d0a4f).

The aspeed-g5.dtsi I use is the same with the one in your link.

I follow your suggestion and add the following to my dts but the SCU0C[8]
is still 1b'.

&lpc_ctrl {
        status = "okay";
};

Even I directly change the status of lpc_ctrl to 'okay'  in the
aspeed-g5.dtsi,  the SCU0C[8] is still 1b'.
lpc_ctrl: lpc-ctrl at 0 {
     compatible = "aspeed,ast2500-lpc-ctrl";
     reg = <0x0 0x80>;
     clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
     status = "okay";
 };

devmem 0x1e6e200c 32
0xFFCDBF8B

Thanks.


2018-06-06 10:36 GMT+08:00 Andrew Jeffery <andrew at aj.id.au>:

> Hi Henbin,
>
> On Wed, 6 Jun 2018, at 11:30, Henbin Chang wrote:
> > Hi,
> >
> > I found 'SCU0C[8] Stop LCLK' was set after boot into Kernel.
> >
> > Could anyone share how/where I should configure the Clock Stop Control
> > Register?
>
> What kernel tree are you building/booting? Can you provide a link?
>
> Currently we've tied the LCLK to enabling LPC2AHB bridge:
>
> https://github.com/openbmc/linux/blob/dev-4.13/arch/arm/
> boot/dts/aspeed-g5.dtsi#L302
>
> You may need to add the following to your dts if you've developed your own:
>
> ```
> &lpc_ctrl {
>         status = "okay";
> };
> ```
>
> Andrew
>
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