How to configure Clock Stop Control Register

[Andrew Jeffery]

Hi Henbin,

On Wed, 6 Jun 2018, at 11:30, Henbin Chang wrote:
> Hi,
> 
> I found 'SCU0C[8] Stop LCLK' was set after boot into Kernel.
> 
> Could anyone share how/where I should configure the Clock Stop Control
> Register?

What kernel tree are you building/booting? Can you provide a link?

Currently we've tied the LCLK to enabling LPC2AHB bridge:

https://github.com/openbmc/linux/blob/dev-4.13/arch/arm/boot/dts/aspeed-g5.dtsi#L302

You may need to add the following to your dts if you've developed your own:

```
&lpc_ctrl {
        status = "okay";
};
```

Andrew