Initial MCTP design proposal

[Naidoo, Nilan]

Hi Jeremy,

The ASPEED does have  hardware support for PCIe VDM via the MCTP Controller block. 

Nilan


-----Original Message-----
From: Jeremy Kerr [mailto:jk at ozlabs.org] 
Sent: Thursday, December 6, 2018 9:07 PM
To: Naidoo, Nilan <nilan.naidoo at intel.com>; openbmc <openbmc at lists.ozlabs.org>
Cc: Supreeth Venkatesh <Supreeth.Venkatesh at arm.com>; David Thompson <dthompson at mellanox.com>; Emily Shaffer <emilyshaffer at google.com>; Dong Wei <Dong.Wei at arm.com>; Andrew Geissler <geissonator at gmail.com>
Subject: Re: Initial MCTP design proposal

Hi Nilan,

Thanks for taking a look.

> As far as the features that need to be supported, we are initially 
> interested in PCIe VDM and SMBus/I2C hardware bindings.

OK, sure thing. Is this on ASPEED hardware?

>   The BMC will also need to be the Bus owner for the interfaces.
>  It is not clear to be yet if we would also need bridging for our 
> initial use cases.

Yes, I think this matches our designs too; I don't see us needing bridging at present.

>   The message types that we need to support are NVMe-SI, PLDM and 
> Vendor Defined - PCI (0x7E). We currently don't have a strong need for 
> supporting the host interface.

Oh, interesting, I didn't expect folks to be using MCTP but not including the host channel. There's no issue with that, so I'll update the wording so it's clear that this can be accommodated.

Cheers,


Jeremy