[PATCH linux dev-4.10] aspeed-g5: add gpiolib irqchip support.
vadimp at mellanox.com
Fri Jun 30 14:44:01 AEST 2017
> -----Original Message-----
> From: openbmc [mailto:openbmc-
> bounces+yanivab=mellanox.com at lists.ozlabs.org] On Behalf Of Andrew
> Sent: Friday, June 30, 2017 4:39 AM
> To: Mykola Kostenok <c_mykolak at mellanox.com>; Joel Stanley
> <joel at jms.id.au>; openbmc at lists.ozlabs.org
> Subject: Re: [PATCH linux dev-4.10] aspeed-g5: add gpiolib irqchip support.
> Hi Mykola,
> On Thu, 2017-06-29 at 16:32 +0300, Mykola Kostenok wrote:
> > To allow support gpio class infrastructure for Aspeed SOC.
> > To allow gpio_to_irq conversion.
> > Enable irqchip and libgpio_irqchip for aspeed-g5.
> > > Signed-off-by: Mykola Kostenok <c_mykolak at mellanox.com>
> > ---
> > arch/arm/mach-aspeed/Kconfig | 3 +++
> > 1 file changed, 3 insertions(+)
> > diff --git a/arch/arm/mach-aspeed/Kconfig
> > b/arch/arm/mach-aspeed/Kconfig index f3f8c5c658db..e098b7a780ee
> > --- a/arch/arm/mach-aspeed/Kconfig
> > +++ b/arch/arm/mach-aspeed/Kconfig
> > @@ -27,6 +27,9 @@ config MACH_ASPEED_G5
> > > depends on ARCH_MULTI_V6
> > > select CPU_V6
> > > select PINCTRL_ASPEED_G5
> > > + select GENERIC_IRQ_CHIP
> > + select GPIOLIB_IRQCHIP
> Sorry, I don't understand the need for this; CONFIG_GPIOLIB_IRQCHIP is
> already selected by CONFIG_GPIO_ASPEED, which is enabled by the
> aspeed_g5_defconfig. I don't think we need to do this here.
> Further, what problem are you trying to solve? From my testing GPIO
> interrupts are functional.
We have the number of CPLDs with the internal interrupt control logic. Interrupts on top routed through the particular GPIO to SoC.
The motivation was to specify top aggregation interrupt for CPLD driver in DTS with GPIO pin number and convert it in driver with gpio_to_irq and connect irq to CPLD interrupt handler.
> > +
> > > help
> > > Say yes if you intend to run on an Aspeed ast2500 or similar
> > > fifth generation Aspeed BMCs.
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