[PATCH linux] Add debounce for power button, pull down gpioQ7 to unlock identify LED

[Adriana Kobylak]

Hi Ken,

Could you reply to Joel if you have any questions about his comments or 
make a new pull request so that the change can be merged? Specifically is 
provide more info regarding the changes, I'm copying the comments here. 
Thanks.


>> From: Ken <ken.sk.lai at mail.foxconn.com>
> We need to include a description of why this change is being made.
> What does it fix? Why does the previous behaviour need to be modified?

>> +       writel(0x00001080, AST_IO(AST_BASE_GPIO | 0x84));
> We have a GPIO driver that handles setting this register.

>> +       writel(0x010FFFFF, AST_IO(AST_BASE_SCU | 0xA8));
> Can you explain each of these you're setting each of these bits?




From:   Joel Stanley <joel at jms.id.au>
To:     OpenBMC Patches <openbmc-patches at stwcx.xyz>, 
ken.th.liu at foxconn.com
Cc:     OpenBMC Maillist <openbmc at lists.ozlabs.org>
Date:   05/12/2016 02:11 AM
Subject:        Re: [PATCH linux] Add debounce for power button, pull down 
gpioQ7 to unlock identify LED
Sent by:        "openbmc" 
<openbmc-bounces+anoo=us.ibm.com at lists.ozlabs.org>



ping

On Mon, May 2, 2016 at 11:12 AM, Joel Stanley <joel at jms.id.au> wrote:
> On Fri, Apr 29, 2016 at 3:10 PM, OpenBMC Patches
> <openbmc-patches at stwcx.xyz> wrote:
>> From: Ken <ken.sk.lai at mail.foxconn.com>
>>
>
> We need to include a description of why this change is being made.
> What does it fix? Why does the previous behaviour need to be modified?
>
>> ---
>>  arch/arm/mach-aspeed/aspeed.c | 8 ++++++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>  mode change 100644 => 100755 arch/arm/mach-aspeed/aspeed.c
>>
>> diff --git a/arch/arm/mach-aspeed/aspeed.c 
b/arch/arm/mach-aspeed/aspeed.c
>> old mode 100644
>> new mode 100755
>> index 594a781..fa5d467
>> --- a/arch/arm/mach-aspeed/aspeed.c
>> +++ b/arch/arm/mach-aspeed/aspeed.c
>> @@ -138,9 +138,10 @@ static void __init do_barreleye_setup(void)
>>         /* GPIO setup */
>>         writel(0x9E82FCE7, AST_IO(AST_BASE_GPIO | 0x00));
>>         writel(0x0370E677, AST_IO(AST_BASE_GPIO | 0x04));
>> -
>> +       writel(0x00001080, AST_IO(AST_BASE_GPIO | 0x84));
>
> We have a GPIO driver that handles setting this register.
>
>>         /* SCU setup */
>>         writel(0x01C00000, AST_IO(AST_BASE_SCU | 0x88));
>> +       writel(0x010FFFFF, AST_IO(AST_BASE_SCU | 0xA8));
>
> Can you explain each of these you're setting each of these bits?
>
>>         /*
>>          * Do read/modify/write on power gpio to prevent resetting 
power on
>> @@ -150,7 +151,10 @@ static void __init do_barreleye_setup(void)
>>         reg |= 0xCFC8F7FD;
>>         writel(reg, AST_IO(AST_BASE_GPIO | 0x20));
>>         writel(0xC738F20A, AST_IO(AST_BASE_GPIO | 0x24));
>> -       writel(0x0031FFAF, AST_IO(AST_BASE_GPIO | 0x80));
>> +       writel(0x0031FF2F, AST_IO(AST_BASE_GPIO | 0x80));
>> +       writel(0x00000001, AST_IO(AST_BASE_GPIO | 0x48));
>> +       writel(0x00000001, AST_IO(AST_BASE_GPIO | 0x4C));
>> +       writel(0x00075300, AST_IO(AST_BASE_GPIO | 0x58));
>
> As above; we have a GPIO driver that handles setting this register.
> Changing these states needs to be done from userspace. See
> https://github.com/openbmc/skeleton/blob/master/bin/Barreleye.py#L531
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