Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC

[Peter Ryser]

It's a little bit more complicated than that but your statement is 
basically correct.

- Peter


Grant Likely wrote:

> On 6/1/06, Peter Ryser <peter.ryser at xilinx.com> wrote:
>
>> There are some silicon issues on the PPC405 in V4 with PVR 0x20011430
>> which are documented in Xilinx solution record 20658. All these issues
>> are fixed in silicon where the PPC405 has a PVR of 0x20011470.
>>
>> Said that it's not true that the caches cannot be used in silicon with
>> PVR 0x20011430. The problem is a corner case which does not show in
>> typical designs.
>
>
> If I understand correctly, the cache issue only shows up with RAM
> attached to the OPB (instead of PLB).  Is that correct?
>
> Cheers,
> g.
>
>