Xilinx hard TEMAC
rick.moleres at xilinx.com
Wed Aug 9 03:58:42 EST 2006
Could you send a system.mhs file from the EDK project you're using so I
can get a bearing on what exactly you have in the hardware? I didn't
think the LL TEMAC could be used without the DMA engine (CDMAC), which
is where the interrupts come from in the Linux/VxWorks drivers I've seen
for this core.
From: David H. Lynch Jr. [mailto:dhlii at dlasys.net]
Sent: Saturday, July 29, 2006 7:09 PM
To: Rick Moleres
Subject: Re: Xilinx hard TEMAC
Rick Moleres wrote:
That is the correct distinction between "soft" and "hard". Just know
that in this case the "soft" TEMAC (whether LL TEMAC or PLB TEMAC) uses
the "hard" TEMAC, and the "hard" TEMAC by itself is not that useful.
First, thanks, your remarks have been enormously helpful.
I have successfully put together a Driver for the TEMAC currently
used in the Pico E-12.
I am still having some difficulty corresponding this TEMAC
implimentation to any of Xilinx's documentation.
It is Exactly the TEMAC supported by the Xilinx uCOSII Treck Web
It seems to be extremely minimal. Basically a DCR interface for most
things that closely matches the GSRD documents.
and TX and RX FIFO's that I can't seem to find documented anywhere,
but I have working based on the Treck WebServer code.
I am have two remaining problems and then I am done.
The first is I am currently doing polled I/O. The transmits
happen as they are requested and the receives are picked up ona a timer
But I am dropping about 50% or more of the receives. I will work
that out myself eventually.
The second is that this driver will serve as the basis for a
driver in other Pico supported OS's. Some of which have no means of
doing Polled Receives.
And I can not get interrupts working. Since my hardware does nto
match anything perfectly - except that Treck Webserver application and
that does not do interrupts.
I am reading all the Xilinx TEMAC Documents and the GSRD documents
reference an IRENABLE register and an IRSTATUS register, I cobbled
assuming that they were access much as the other DCR registers in
that block and I assumed the bits in IRSTATUS and IRENABLE matched the
definitions of those
in larger TEMAC implimentations. It appeared after I enabled TX and
RX complete interrupts that when I have received data available the
IRSTATUS register has the
Bit set for an Rx interrupt. All fine - except that no interrupt
I can force interrupts from the PHY using the same IRQ so the IRQ is
connected correctly and programmed correctly. Other TEMAC
implimentations seem to have a GIE - Global Interrupt enable
Bit, but I do not have a clue where to look here. What I could get
out of the Xilinx Webset GSRD seems to be a Linux driver that uses the
DMA unit and that generates its own interrupts.
I don't think I have the DMA in my bit image.
Anyway any clues as to where I can find some useful docs on
Interrupt handling for the LL_TEMAC that is used by the uCOSII WebServer
Thereis a Linux driver for the LL_TEMAC that comes with GSRD, but my
group's efforts go toward the PLB_TEMAC as that is the EDK IP we want to
promote and whose drivers we'd like to see in kernel.org.
You should be able to go to http://www.xilinx.com/gsrd to get the GSRD
design, and inside of that design somewhere you'll find a Linux 2.4
driver for the LL TEMAC.
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Dave Lynch DLA Systems
Software Development: Embedded Linux
717.627.3770 dhlii at dlasys.net http://www.dlasys.net
fax: 1.253.369.9244 Cell: 1.717.587.7774
Over 25 years' experience in platforms, languages, and technologies too
numerous to list.
"Any intelligent fool can make things bigger and more complex... It
takes a touch of genius - and a lot of courage to move in the opposite
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