CPM2 early console

Dan Malek dan at embeddedalley.com
Wed Sep 28 06:48:21 EST 2005

On Sep 27, 2005, at 4:35 PM, Kalle Pokki wrote:

> OK. Then the question really is why isn't the cache controller 
> enforcing coherency between the G2_LE core and the CPM.

Is the GBL and DTB set properly in the function code registers
of the SCC parameter ram?

	-- Dan

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