Problem with data cache on MPC823E

[Wolfgang Denk]

In message <3E2D751C.7000001 at devcom.cz> you wrote:
>
> we have developed our board with MPC823E, FLASH memory
> DRAM memory for embedded Linux porting, but we have problem
> with data cache. From time to time when CPU wants load data from DRAM
> to data cache, it makes four burst-reads instead of one for loading one
> cache line.
> After this, all four words in cache line are loaded with the same first
> "critical word".
> We don't know, why CPU repeats this burst-read four times. May be it is
> because we have floating BI (burst inhibit) CPU singnal.
> We have set BIH bit in UPMA to zero.
> When setting this BIH bit to one (burst inhibit), all works well.
> Does anybody have any help ?

This pheomenon is typical for bad SDRAM initialization. Read the chip
manufacturer's manual and follow  the  steps  of  the  init  sequence
_to_the_letter_. It is _not_ sufficient to set up the UPM tables.

Best regards,

Wolfgang Denk

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Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
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