External TA assertion timing on GPCM

Navin Boppuri navin.boppuri at newisys.com
Wed Mar 27 03:44:56 EST 2002

Thanks guys. The answer was very helpful.


-----Original Message-----
From: Steven Scholz [mailto:steven.scholz at imc-berlin.de]
Sent: Monday, March 25, 2002 1:55 AM
To: Navin Boppuri
Cc: Ppcboot-Users (E-mail); Linuxppc-Embedded (E-mail)
Subject: Re: External TA assertion timing on GPCM


I quotr from MPC860 User Man. Chapter 11.6 Bus Monitor
"...The timing mechanism is clocked by the system clock devided by
eight. The maximum value is 2040 system clocks..."

The bus monitor timing is set in Bits 16-23 of SYPCR.

Hope this helps,


>I would like to know if there is a maximum limit from the time CS is asserted (during a read/write operation) till TA is asserted by the device externally.

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