Software Emulation Kernel Panic--specific information

Lucinda Schafer lucsch at
Thu Jun 22 05:52:23 EST 2000

We came across this before and got all excited until we looked at our mask
revision (3H97G) and searched through the errata. That particular errata is
no longer listed (I thought, though,it is CPU6, not CPU5). There is a fix
(or workaround) for CPU6 in the Montavista kernel. So far that hasn't fixed
our problem, though.

Thanks for all your ideas.

Lucinda Schafer
Staff Software Engineer
Adaptive Micro-Ware, Inc.

-----Original Message-----
From: diekema at [mailto:diekema at]
Sent: Wednesday, June 21, 2000 2:29 PM
To: lucsch at
Subject: Re: Software Emulation Kernel Panic--specific information

This should help...

>From wd at Sat Feb 26 19:57:50 2000
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To: diekema at (diekema_jon)
From: Wolfgang Denk <wd at>
Subject: Re: vs. I think I found the problem
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Status: OR

On the other hand, while this obviously was  the  immediate  problem,
I'm not sure if you now will be much luckier. These other crashes are
not explained by the bad IP address.

And I have similar problems when running  a  more  extensive  set  of
tests on my module. Problems which look very familiar to me... :-(

I'm reading a Microprocessor Mask Set of 0160 in my IMMR - which is a
bit strange, since it  is  not  listed  in  the  Motorola  docs  (for
instance; but
the  printing  on  the  chip reads "XPC860TZP50B5", which indicates a
B.5/3J21M  mask  -   and   the   errata   sheet   (MPC860err.pdf   on   still  con-
tains the CPU Bug #5: "Possible Data Cache  Corruption  When  Writing

This is a known problem, and it will KILL you during context switches
and/or interrupts with any OS which uses the MMU with virtual  memory
- including Linux.

Please check your CPU - I'm afraid that TQ shipped you old CPU,  too.
If this should be the case you need to get a replacement, because you
will  never  be  able to run a normal Linux with full speed on such a
system. [As a workaround and for verification that this is indeed the
problem,  you  can  disable  the   data   cache   -   please   modify
arch/ppc/kernel/head.S as follows:

--- arch/ppc/kernel/head.S.OLD	Tue Feb 15 01:10:40 2000
+++ arch/ppc/kernel/head.S	Sun Feb 27 01:49:16 2000
@@ -425,14 +425,6 @@
 	mtspr	IC_CST, r8
 #if 0
 	mtspr	DC_CST, r8
-	/* For a debug option, I left this here to easily enable
-	 * the write through cache mode
-	 */
-	lis	r8, DC_SFWT at h
-	mtspr	DC_CST, r8
-	lis	r8, IDC_ENABLE at h
-	mtspr	DC_CST, r8

 /* We now have the lower 8 Meg mapped into TLB entries, and the caches

This will completely disable the data cache. You system will be a bit
slower than normal, but it should not crash any more.]

Seems we found both a software bug *and* a hardware problem :-(

I'm sorry, but I don't have any better news for you.

Wolfgang Denk

Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at
In C we had to code our own bugs, in C++ we can inherit them.

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