Looking for architecture papers

[Gabriel Paubert]

On Thu, Oct 04, 2018 at 10:41:13AM +0300, Raz wrote:
> Frankly, the more I read the more perplexed I get. For example,
> according to BOOK III-S, chapter 3,
> the MSR bits are differ from the ones described in
> arch/powerpc/include/asm/reg.h.
> Bit zero, is LE, but in the book it is 64-bit mode.

Just a problem of bit order definitions: IBM hardware definitions use
big-endian bit ordering, where bit 0 is the most significant bit.

> 
> Would someone be kind to explain what I do not understand?
> 
> Thank you

	Gabriel