[PATCH 2/2] Make the diu driver work without board level initilization
Dongsheng.Wang at freescale.com
Dongsheng.Wang at freescale.com
Tue Apr 1 13:42:01 EST 2014
> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+b40534=freescale.com at lists.ozlabs.org] On Behalf Of Jason Jin
> Sent: Thursday, March 27, 2014 7:38 PM
> To: Wood Scott-B07421; timur at tabi.org
> Cc: linux-fbdev at vger.kernel.org; linuxppc-dev at lists.ozlabs.org; Li Yang-Leo-
> R58472; Jin Zhengxiong-R64188
> Subject: [PATCH 2/2] Make the diu driver work without board level initilization
>
> So far the DIU driver does not have a mechanism to do the
> board specific initialization. So on some platforms,
> such as P1022, 8610 and 5121, The board specific initialization
> is implmented in the platform file such p10222_ds.
>
> Actually, the DIU is already intialized in the u-boot, the pin sharing
> and the signal routing are also set in u-boot. So we can leverage that
> in kernel driver to avoid board sepecific initialization, especially
> for the corenet platform, which is the abstraction for serveral
> platfroms.
>
> The potential problem is that when the system wakeup from the deep
> sleep, some platform settings may need to be re-initialized. The CPLD
> and FPGA settings will be kept, but the pixel clock register which
> usually locate at the global utility space need to be reinitialized.
>
> Generally, the pixel clock setting was implemented in the platform
> file, But the pixel clock register itself should be part of the DIU
> module, And for P1022,8610 and T1040, the pixel clock register have the
> same structure, So we can consider to move the pixel clock setting
> from the platform to the diu driver. This patch provide the options
> set the pixel clock in the diu driver. But the original platform pixel
> clock setting stil can be used for P1022,8610 and 512x without any
> update. To implement the pixel clock setting in the diu driver. the
> following update in the diu dts node was needed.
> display:display at 180000 {
> compatible = "fsl,t1040-diu", "fsl,diu";
> - reg = <0x180000 1000>;
> + reg = <0x180000 1000 0xfc028 4>;
> + pixclk = <0 255 0>;
> interrupts = <74 2 0 0>;
> }
> The 0xfc028 is the offset for pixel clock register. the 3 segment of
> the pixclk stand for the PXCKDLYDIR, the max of PXCK and the PXCKDLY
> which will be used by the pixel clock register setting.
>
> This was tested on T1040 platform. For other platform, the original
> node together with the platform settings still can work.
>
> Signed-off-by: Jason Jin <Jason.Jin at freescale.com>
> ---
> V2: Remove the pixel clock register saving for suspend.
> add the pixel clock setting in driver.
>
> drivers/video/fsl-diu-fb.c | 61 ++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 59 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
> index 4bc4730..792038f 100644
> --- a/drivers/video/fsl-diu-fb.c
> +++ b/drivers/video/fsl-diu-fb.c
> @@ -50,6 +50,7 @@
> #define INT_PARERR 0x08 /* Display parameters error interrupt */
> #define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
>
> +#define PIXCLKCR_PXCKEN 0x80000000
> /*
> * List of supported video modes
> *
> @@ -372,6 +373,8 @@ struct fsl_diu_data {
> unsigned int irq;
> enum fsl_diu_monitor_port monitor_port;
> struct diu __iomem *diu_reg;
> + void __iomem *pixelclk_reg;
> + u32 pixclkcr[3];
> spinlock_t reg_lock;
> u8 dummy_aoi[4 * 4 * 4];
> struct diu_ad dummy_ad __aligned(8);
> @@ -479,7 +482,10 @@ static enum fsl_diu_monitor_port fsl_diu_name_to_port(const
> char *s)
> port = FSL_DIU_PORT_DLVDS;
> }
>
> - return diu_ops.valid_monitor_port(port);
> + if (diu_ops.valid_monitor_port)
> + return diu_ops.valid_monitor_port(port);
> + else
Remove this "else", otherwise looks good.
Regards,
-Dongsheng
> + return port;
> }
>
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