[RFC][PATCH v5] MPC5121 TLB errata workaround

[Kenneth Johansson]

On Mon, 2009-03-16 at 16:52 +0100, David Jander wrote:
> Complete workaround for DTLB errata in e300c2/c3/c4 processors.
> 
> Due to the bug, the hardware-implemented LRU algorythm always goes to way
> 1 of the TLB. This fix implements the proposed software workaround in
> form of a LRW table for chosing the TLB-way.
> 
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> Signed-off-by: David Jander <david at protonic.nl>

I think we have a winner. with one instruction slot left :)
I tried your V4 and V5 and could not see any difference in speed.


Acked-by: Kenneth Johansson <kenneth at southpole.se>