[RFC][PATCH v5] MPC5121 TLB errata workaround

[Kumar Gala]

On Mar 16, 2009, at 10:52 AM, David Jander wrote:

> Complete workaround for DTLB errata in e300c2/c3/c4 processors.
>
> Due to the bug, the hardware-implemented LRU algorythm always goes  
> to way
> 1 of the TLB. This fix implements the proposed software workaround in
> form of a LRW table for chosing the TLB-way.
>
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> Signed-off-by: David Jander <david at protonic.nl>
>
> ---
> diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/ 
> head_32.S
> index 0f4fac5..3971ee4 100644
> --- a/arch/powerpc/kernel/head_32.S
> +++ b/arch/powerpc/kernel/head_32.S
> @@ -578,9 +578,21 @@ DataLoadTLBMiss:
> 	andc	r1,r3,r1		/* PP = user? (rw&dirty? 2: 3): 0 */
> 	mtspr	SPRN_RPA,r1
> 	mfspr	r3,SPRN_DMISS
> +	mfspr	r2,SPRN_SRR1		/* Need to restore CR0 */
> +	mtcrf	0x80,r2
> +#ifdef CONFIG_PPC_MPC512x
> +	li	r0,1
> +	mfspr	r1,SPRN_SPRG6
> +	rlwinm	r2,r3,17,27,31		/* Get Address bits 19:15 */

Don't we want:
	rlwinm	r2,r3,20,27,31		/* Get address bits 15:19 */

> +	slw	r0,r0,r2
> +	xor	r1,r0,r1
> +	srw	r0,r1,r2
> +	mtspr   SPRN_SPRG6,r1
> +	mfspr	r2,SPRN_SRR1
> +	rlwimi	r2,r0,31-14,14,14
> +	mtspr   SPRN_SRR1,r2
> +#endif
> 	tlbld	r3
> -	mfspr	r3,SPRN_SRR1		/* Need to restore CR0 */
> -	mtcrf	0x80,r3
> 	rfi

- k