Broken PCI on Sequoia
benh at kernel.crashing.org
Sat Jan 31 08:30:24 EST 2009
> For that sort of 4xx PHB (ie, the PCI 2.x ones, not the PCI-X nor the
> PCI-E), we only know how to program 32-bit of PLB address. IE. The old
> code would have cropped the plb_addr when writing to the register, the
> new code complains.
> I suspect some implementation support a register to put the "high" part
> of the PLB address, and that it already contains 1, so the old code
> would have worked by chance, the new code doesn't because it bails out.
Hrm... from the doco it's also one 32-bit register... I'm starting to
think that those guys always assume the top 1 bit is set or something
like that ...
The doc is unclear. Maybe somebody form AMCC can confirm ?
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