[PATCH 0/2] [PPC 4xx] L2-cache synchronization for ppc44x
ebs at ebshome.net
Sat Jan 12 04:41:52 EST 2008
On Fri, Jan 11, 2008 at 06:24:46PM +0300, Yuri Tikhonov wrote:
> Hello, Eugene,
> The h/w snooping mechanism you are talking about is limited to the Low
> Latency (LL) segment of the PLB bus in ppc440sp and ppc440spe chips (see
> section "7.2.7 L2 Cache Coherency" of the ppc440spe spec), whereas DMA and
> XOR engines use the High Bandwidth (HB) segment of PLB bus (see
> section "1.1.2 Internal Buses" of the ppc440spe spec).
> Thus, the h/w snooping mechanism is not able to trace the results of
> operations performed by DMA and XOR engines and keep L2-cache coherent with
> SDRAM, because the data flow through the HB PLB segment. This leads to, for
> example, incorrect results of RAID-parity calculations if one uses the h/w
> accelerated ppc440spe ADMA driver with L2-cache enabled.
> The s/w synchronization algorithms proposed in my patches has no LL PLB
> limitations as opposed to h/w snooping, but, probably, this is not the best
> way of how it might be implemented. Even though with these patches the h/w
> accelerated RAID starts to operate correctly (with L2-cache enabled) there is
> a performance degradation (induced by loops in the L2-cache synchronization
> routines) observed in the most cases. So, as a result, there is no benefit
> from using L2-cache for these, RAID, cases at all.
Thanks a lot for explanation, Yuri. I'd never imagine they were so
stupid to make new chips with such behaviour.
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