Problems in 2.6 memory management on 8xx

[Joakim Tjernlund]

On Thu, 2007-05-24 at 17:23 +0200, Joakim Tjernlund wrote:
> On Thu, 2007-05-24 at 15:07 +0200, Detlev Zundel wrote:
> > Hi,
> > 
> > working on a 2.6.16 kernel on a 870 CPU, I ran into this strange
> > behaviour exemplified by the simple attached demo program.  An icbi
> > from userspace on an address that is mapped only lazily gets into an -
> > though interruptible - loop. Locking the icbi target in question with
> > mlock circumvents this problem.
> 
> 8xx is buggy w.r.t cache instructions. They do not update the
> DAR register in the TLB miss/TLB error handlers.
> The TLB miss handler does not use the DAR reg but the TLB error
> handler do. Thats why it works when you mlock the memory.
> 
> This bug isn't documented but Freescale has confirmed it.
> You can search the archives some years back for more info.
> 
>  Jocke

BTW, it is possible to workaround this problem in the kernel by
tagging DAR with an impossible value and compare DAR against it
in the DTLB Error handler. If a match, then do a instruction decode
to get the regs involved and calculate the faulting address.

I did this several years ago for 2.4 in assembler and posted
it, but it was rejected.
One should bail out to handle_page_fault and do the
calculations there instead(less likely to break that way)

Found one version of the patch here:
http://patchwork.ozlabs.org/linuxppc/patch?id=1307

 Jocke