[PATCH] Remove CPU_FTR_NEED_COHERENT for 7448.

[Benjamin Herrenschmidt]

On Thu, 2007-05-03 at 10:17 +0000, Adrian Cox wrote:
> On Wed, 2007-05-02 at 16:34 -0500, Jon Loeliger wrote: 
> > From: James.Yang <James.Yang at freescale.com>
> > 
> > Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx).
> > This prevents needlessly setting M=1 when not SMP.
> 
> There may be side effects to removing this. Most of the 74xx processors
> had this flag added because of the L2 prefetch bug (erratum #16 on the
> 7447A). I see that bug is missing from the 7448 errata.
> 
> The problem is that many 32-bit PowerPC machines needed
> CPU_FTR_NEED_COHERENT set for a second reason: compatibility with the
> cache in the MPC107. This was handled by CPU_FTR_COMMON in cputable.h
> before the L2 prefetch bug was known.  There may be other host bridges
> that cache, but nobody will have noticed because all the CPUs had
> CPU_FTR_NEED_COHERENT set already.

There are a few options there...

The feature fixup and the hash table init are done after machine probe,
so the machine probe routine can do some last minute fixups of the
features, like detecting an MPC107 or whatever..

Another option would be to add a bit of generic code in
early_init_devtree() to detect the MPC107 and set that feature bit when
it's present, but that would involve having a consistent way to
recognize it via the device-tree which might not be the case currently
(though that only matters for 7448 based-boards so it's still doable).

Cheers,
Ben.