[PATCH] Remove CPU_FTR_NEED_COHERENT for 7448.

[Jon Loeliger]

On Thu, 2007-05-03 at 05:17, Adrian Cox wrote:
> On Wed, 2007-05-02 at 16:34 -0500, Jon Loeliger wrote: 
> > From: James.Yang <James.Yang at freescale.com>
> > 
> > Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx).
> > This prevents needlessly setting M=1 when not SMP.
> 
> There may be side effects to removing this. Most of the 74xx processors
> had this flag added because of the L2 prefetch bug (erratum #16 on the
> 7447A). I see that bug is missing from the 7448 errata.
> 
> The problem is that many 32-bit PowerPC machines needed
> CPU_FTR_NEED_COHERENT set for a second reason: compatibility with the
> cache in the MPC107. This was handled by CPU_FTR_COMMON in cputable.h
> before the L2 prefetch bug was known.  There may be other host bridges
> that cache, but nobody will have noticed because all the CPUs had
> CPU_FTR_NEED_COHERENT set already.

Adrian,

Yes, you are correct and your concern is valid.  However,
this case is still being handled by CONFIG_MPC10X_BRIDGE
to deal with the MPC106/MPC107/etc north bridges.

Here:
    include/asm-powerpc/cputable.h:183

/* We need to mark all pages as being coherent if we're SMP or we
 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
 * it for PCI "streaming/prefetch" to work properly.
 */
#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
	|| defined(CONFIG_PPC_83xx)
#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
#else
#define CPU_FTR_COMMON                  0
#endif

The CPU doesn't impose this requirement, the north bridge does.
It might even better be named something like
    CPU_FTR_NORTHBRDIGE_NEEDS_COHERENT.

Thanks,
jdl