[PATCH] ppc32: Fix alignment exception checking on load/store multiple instructions

[Kumar Gala]

>  > > The handling of misaligned load/store multiplies did not check to 
> see
>  > > if
>  >  > the address were ok to access before __{get,put}_user().
> >
>  > I think we should also take the opportunity to fix up the lawrx
> > case and look for other reserved/conditional instructions
>  >  that may slip through.  Since these are atomic operations, we
> > can't emulate them.  According to the PEM, an alignment fault
> > on these is a fatal programming error.
>
> When you say "fix up" I assume you mean lwarx should return 0.  It
> appears that stwcx. is already doing that.  Can't think of any other
> cases that need fixing.

Upon further review, the PEM and PPC Arch spec, say that its ok to 
emulate lwarz as an lwz.  From the spec:

The instructions lwz and lwarx give the same DSISR bits (all zero). But 
if lwarx causes an Alignment interrupt, it should not be emulated. It 
is adequate for the Alignment interrupt handler simply to treat the 
instruction as if it were lwz. The emulator
must use the address in the DAR, rather than compute it from RA/RB/D, 
because lwz and lwarx have different instruction formats.

So we are handled lwarx according to the arch specs already.

- kumar