[PATCH] ppc32: Fix alignment exception checking on load/store multiple instructions

[Dan Malek]

On Apr 12, 2005, at 11:26 AM, Kumar Gala wrote:

> Upon further review, the PEM and PPC Arch spec, say that its ok to 
> emulate lwarz as an lwz.  From the spec:

Hmmm ...  Seems weird.  Since the emulation won't create the 
reservation,
the subsequent stwcx will fail.  If the stwcx to the same unaligned 
address
will be a programming error.

Also, the EREF states that neither the lwarx nor stwcx should be 
emulated,
and it's a programming error to have unaligned accesses with these.
I still don't like this "similar but different" Book-E architecture, 
but I guess
we have to live with it ....


> The instructions lwz and lwarx give the same DSISR bits (all zero). 
> But if lwarx causes an Alignment interrupt, it should not be emulated.

???  Those are nearly the same words from the EREF, I just didn't find 
anything
like the following.

> ... It is adequate for the Alignment interrupt handler simply to treat 
> the instruction as if it were lwz. The emulator
> must use the address in the DAR, rather than compute it from RA/RB/D, 
> because lwz and lwarx have different instruction formats.

I guess it's done as lwz because it's not possible to actually emulate 
an
unaligned lwarx?

> So we are handled lwarx according to the arch specs already.

If that's the way you read it :-)   Probably not worth the discussion, 
but
I brought it up since we are here and it will be soon forgotten.

Thanks.


	-- Dan