[Cbe-oss-dev] [patch 11/11] powerpc/cell: Add DMA_ATTR_STRONG_ORDERING dma attribute and use in IOMMU code

[Benjamin Herrenschmidt]

On Sat, 2008-07-05 at 23:51 +0200, Arnd Bergmann wrote:
> 
> It turned out that the firmware sets up the south bridge to never set the 'S'
> bit on incoming transactions, which overrides the IOPTE_SO_RW bits, on all
> existing cell hardware.
> 
> This weak ordering gives the same ordering guarantees as the default ordering
> for DMA on other PowerPC machines. Setting strong ordering on both the host
> bridge *and* the page table will give further ordering guarantees, i.e.
> it will make sure that no DMA requests on the bus can ever overtake each
> other

I need to look closely at what the various bridge settings are. Drivers
do expect DMA requests from one device to stay in order, at least up to
what's defined in the PCI spec, which is pretty much fully ordered
unless those devices set the PCIe (or X) relaxed ordering attribute.
However, AFAIK, Axon doesn't convey that sort of ordering attributes
from incoming transactions between the PCIe segment and the PLB5.

Ben.