[Cbe-oss-dev] [patch 11/11] powerpc/cell: Add DMA_ATTR_STRONG_ORDERING dma attribute and use in IOMMU code

[Arnd Bergmann]

On Saturday 05 July 2008, Benjamin Herrenschmidt wrote:
> On Sat, 2008-07-05 at 15:43 +1000, Michael Ellerman wrote:
> > > The current Cell IOMMU implementation sets the IOPTE_SO_RW bits in all IOTPEs
> > > (for both the dynamic and fixed mappings) which enforces strong ordering of
> > > both reads and writes. This patch makes the default behaviour weak ordering
> > > (the IOPTE_SO_RW bits not set) and to request a strongly ordered mapping the
> > > new DMA_ATTR_STRONG_ORDERING needs to be used.
> > 
> > We're sure that's safe?
> 
> I'd say it's not...

It turned out that the firmware sets up the south bridge to never set the 'S'
bit on incoming transactions, which overrides the IOPTE_SO_RW bits, on all
existing cell hardware.

This weak ordering gives the same ordering guarantees as the default ordering
for DMA on other PowerPC machines. Setting strong ordering on both the host
bridge *and* the page table will give further ordering guarantees, i.e.
it will make sure that no DMA requests on the bus can ever overtake each
other.

	Arnd <><