[Cbe-oss-dev] [RFC/PATCH] adding support for direct MBX interrupt on Axon based platform.

[Jean-Christophe Dubois]

On Saturday 19 May 2007 11:16:47 Arnd Bergmann wrote:
> On Saturday 19 May 2007, Benjamin Herrenschmidt wrote:
> > On Sat, 2007-05-19 at 10:22 +0200, Arnd Bergmann wrote:
> > > Defining c3p0 as a cascaded IRQ controller is only necessary
> > > if we can't use the class number.
> >
> > I'm not even sure it would help... you can't go read on the C3PO where
> > the IRQ came from or anything like that. It's just purely a bridge afaik
> > converting the 4 Axon internal interrupt into BE interrupt messages.
>
> Right, unless we change the logic to pass down the priority value to
> the cascade handler, which would still be better than adding specific
> hacks to the internal interrupt code.
>
> An alternative could be to make it a shared interrupt, so that we first
> check if an interrupt came in through the mailbox, and only look
> at the mpic if the interrupt wasn't handled yet.

There is no status to check that a MBX was emitted on the C3PO. You could 
check on the MBX itself if the write pointer was changed from last time but I 
am not sure it really belongs to the interrupt generic code.

The MBX direct interrupt is just a pulse type interrupt and does not require 
acknowledge or anything similar. It is just a notification.

JC

>
> 	Arnd <><
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