[Skiboot] [PATCH v2 44/59] xive/p10: Activate split mode for PHB ESBs when PQ_disable is available

[Vasant Hegde]

From: Cédric Le Goater <clg at kaod.org>

1/3rd of the cache is reserved for PHB ESBs and the rest to IPIs.
This is sufficient to keep all the PHB ESBs in cache and avoid ESB
cache misses during IO interrupt processing.

Signed-off-by: Cédric Le Goater <clg at kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant at linux.vnet.ibm.com>
---
 hw/xive2.c           | 25 +++++++++++++++++++++++++
 include/xive2-regs.h |  5 +++++
 2 files changed, 30 insertions(+)

diff --git a/hw/xive2.c b/hw/xive2.c
index 2291e9379..0f9c93d6a 100644
--- a/hw/xive2.c
+++ b/hw/xive2.c
@@ -1602,6 +1602,29 @@ static bool xive_cfg_save_restore(struct xive *x)
 	return !!(x->config & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE);
 }
 
+/*
+ * When PQ_disable is available, configure the ESB cache to improve
+ * performance for PHB ESBs.
+ *
+ * split_mode :
+ *   1/3rd of the cache is reserved for PHB ESBs and the rest to
+ *   IPIs. This is sufficient to keep all the PHB ESBs in cache and
+ *   avoid ESB cache misses during IO interrupt processing.
+ */
+static void xive_config_esb_cache(struct xive *x)
+{
+	uint64_t val = xive_regr(x, VC_ESBC_CFG);
+
+	if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) {
+		val |= VC_ESBC_CFG_SPLIT_MODE;
+		xive_dbg(x, "ESB cache configured with split mode. "
+			 "VC_ESBC_CFG=%016llx\n", val);
+	} else
+		val &= ~VC_ESBC_CFG_SPLIT_MODE;
+
+	xive_regw(x, VC_ESBC_CFG, val);
+}
+
 static void xive_config_fused_core(struct xive *x)
 {
 	uint64_t val = xive_regr(x, TCTXT_CFG);
@@ -1717,6 +1740,8 @@ static bool xive_config_init(struct xive *x)
 
 	xive_config_fused_core(x);
 
+	xive_config_esb_cache(x);
+
 	xive_config_reduced_priorities_fixup(x);
 
 	return true;
diff --git a/include/xive2-regs.h b/include/xive2-regs.h
index ad1a9b79f..4638c3d89 100644
--- a/include/xive2-regs.h
+++ b/include/xive2-regs.h
@@ -227,6 +227,11 @@
 #define  VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK	PPC_BITMASK(32,35)
 #define  VC_ESBC_FLUSH_POLL_OFFSET_MASK		PPC_BITMASK(36,63) /* 28-bit */
 
+/* ESBC configuration */
+#define X_VC_ESBC_CFG				0x148
+#define VC_ESBC_CFG				0x240
+#define	 VC_ESBC_CFG_SPLIT_MODE			PPC_BIT(56)
+
 /* EASC flush control register */
 #define X_VC_EASC_FLUSH_CTRL			0x160
 #define VC_EASC_FLUSH_CTRL			0x300
-- 
2.31.1