[Skiboot] [PATCH v5] hw/npu2-opencapi: Add initial support for allocating OpenCAPI LPC memory

Stewart Smith stewart at linux.ibm.com
Tue May 21 13:18:25 AEST 2019

Andrew Donnellan <ajd at linux.ibm.com> writes:
> Lowest Point of Coherency (LPC) memory allows the host to access memory on
> an OpenCAPI device.
> assigning and clearing the memory BAR. (We try to avoid using the term
> "LPC" to avoid confusion with Low Pin Count.)
> At present, we use a fixed location in the address space, which means we
> are restricted to a single range of 4TB, on a single OpenCAPI device per
> chip. In future, we'll use some chip ID extension magic to give us more
> space, and some sort of allocator to assign ranges to more than one device.
> Signed-off-by: Andrew Donnellan <ajd at linux.ibm.com>
> ---
> This code is currently being used for some internal testing of LPC memory
> devices and seems to work acceptably for that purpose. We haven't tested
> all the corner cases... this is really just intended to enable prototyping
> and bringup at this stage.

Merged to master as of 1a548857ce1f02f43585b326a891eed18a7b43b3.

One open question we have is how we deal with these new OPAL APIs that
may need some further stabilisation before being ready for
prime-time. Seeing as a skiboot 6.4 is probably a bit off, we have a
window here, but we might want to think about what we do into the
future. An NVRAM option to enable them (meh)? An ifdef (yuck)?

Stewart Smith
OPAL Architect, IBM.

More information about the Skiboot mailing list