[Skiboot] [PATCH v2 1/6] xive: Remove xive rev field and recognize P9P

[Cédric Le Goater]

On 5/6/19 8:28 AM, Oliver wrote:
> On Thu, May 2, 2019 at 9:17 PM Nicholas Piggin <npiggin at gmail.com> wrote:
>>
>> All supported P9s are the revision 2 xive model, so there is no point
>> to keeping it around. This avoids P9P being reported as unknown rev
>> (which doesn't cause any other problems).
>>
>> Signed-off-by: Nicholas Piggin <npiggin at gmail.com>
Reviewed-by: Cédric Le Goater <clg at kaod.org>

>> ---
>>  hw/xive.c | 23 ++++++++++++-----------
>>  1 file changed, 12 insertions(+), 11 deletions(-)
>>
>> diff --git a/hw/xive.c b/hw/xive.c
>> index f38226523..5edcaedf5 100644
>> --- a/hw/xive.c
>> +++ b/hw/xive.c
>> @@ -365,10 +365,6 @@ struct xive {
>>         uint32_t        chip_id;
>>         uint32_t        block_id;
>>         struct dt_node  *x_node;
>> -       int             rev;
>> -#define XIVE_REV_UNKNOWN       0       /* Unknown version */
>> -#define XIVE_REV_1             1       /* P9 (Nimbus) DD1.x (not supported) */
>> -#define XIVE_REV_2             2       /* P9 (Nimbus) DD2.x or Cumulus */
> 
> 
> IIRC Pn+1 is going to have rev 3 XIVE. Are you sure we're not going to
> end up adding this again later on?

These XIVE revision numbers are related to the processor revision numbers. 
P9 implements the XIVE Gen1 architecture. So we had a XIVE-1.1 and a XIVE-1.2. 
As we removed support for the P9 DD1.x, it makes sense to remove also the 
XIVE1.1 define.

XIVE Gen2 (P10) has a different HW interface and we will introduce a new 
driver for it.

This is similar to the PHBs : 

  ...
  P8  - PHB3 - XICS
  P9  - PHB4 - XIVE1
  P10 - PHB5 - XIVE2
  ...

Thanks,

C.

> 
>> @@ -2836,15 +2832,20 @@ static struct xive *init_one_xive(struct dt_node *np)
>>         chip = get_chip(x->chip_id);
>>         assert(chip);
>>
>> -       x->rev = XIVE_REV_UNKNOWN;
>> -       if (chip->type == PROC_CHIP_P9_NIMBUS) {
>> +       /* All supported P9 are revision 2 (Nimbus DD2) */
>> +       switch (chip->type) {
>> +       case PROC_CHIP_P9_NIMBUS:
>> +               /* We should not be able to boot a P9N DD1 */
>>                 assert((chip->ec_level & 0xf0) != 0x10);
>> -               x->rev = XIVE_REV_2;
>> -       } else if (chip->type == PROC_CHIP_P9_CUMULUS)
>> -               x->rev = XIVE_REV_2;
>> +               /* Fallthrough */
>> +       case PROC_CHIP_P9_CUMULUS:
>> +       case PROC_CHIP_P9P:
>> +               break;
>> +       default:
>> +               assert(0);
>> +       }
>>
>> -       xive_dbg(x, "Initializing rev %d block ID %d...\n",
>> -                x->rev, x->block_id);
>> +       xive_dbg(x, "Initializing block ID %d...\n", x->block_id);
>>         chip->xive = x;
>>
>>  #ifdef USE_INDIRECT
>> --
>> 2.20.1
>>
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