[Skiboot] [PATCH] Add in new OPAL call to flush the L2 and L3 caches.

[Alexey Kardashevskiy]

On 02/11/2018 15:19, Rashmica Gupta wrote:
> On Fri, 2018-11-02 at 14:14 +1100, Alexey Kardashevskiy wrote:
>>>>>
>>
>> On 02/11/2018 13:48, Rashmica Gupta wrote:
>>> On Fri, 2018-11-02 at 13:17 +1100, Alexey Kardashevskiy wrote:
>>>>
>>>> On 29/10/2018 17:19, Rashmica Gupta wrote:
> 
> ...
> 
>>>>>
>>>>> +static int flush_l2_caches(uint32_t chip_id, uint32_t core_id)
>>>>> +{
>>>>> +	int rc, timeout = 0;
>>>>> +	unsigned long start_time;
>>>>> +	uint64_t val = L2_PRD_PURGE_CMD_REG_BUSY;
>>>>> +	uint64_t addr = XSCOM_ADDR_P9_EX(core_id,
>>>>> L2_PRD_PURGE_CMD_REG);
>>>>> +
>>>>> +	rc = xscom_write_mask(chip_id, addr,
>>>>> L2_PRD_PURGE_CMD_TRIGGER,
>>>>> +			      L2_PRD_PURGE_CMD_TRIGGER);
>>>>
>>>> The advise from the hw folks was:
>>>>
>>>>  putspy pu.ex EXP.L2.L2MISC.L2CERRS.PRD_PURGE_CMD_TYPE
>>>> L2CAC_FLUSH
>>>> -all
>>>>
>>>>  putspy pu.ex EXP.L2.L2MISC.L2CERRS.PRD_PURGE_CMD_TRIGGER ON -all
>>>>
>>>> I can see trigger action but not L2CAC_FLUSH.
>>>>
>>>
>>> I lumped them together (as L2CAC_FLUSH=>0b0000). I'll split it up
>>> and
>>> make it clearer though.
>>
>>
>> Ah, my bad, I was reading it as 0x0b0000 and was looking for 'b'
>> :)Anyway, useful to see them defined somewhere. Also, can it be a
>> single
>> write to the register (looks like it can and then there is no need to
>> separation) or should it be 2 writes as the hw folks strangely
>> suggested?
> 
> I assumed that it would be fine to write the type of flush and trigger
> it at the same time... But their suggestion did have them seperate, so 
> maybe I should do it like that just to be safe?


I suggest asking Alistair the expert  :)


-- 
Alexey