[Skiboot] [PATCH 1/2] npu2-opencapi: Fix 'link internal error' FIR, take 1

[Frederic Barrat]

When we setup a link, we always enable ODL0 and ODL1 at the same time
in the PHY training config register, even though we are setting up
only one OTL/ODL, so it raises a "link internal error" FIR bit in the
PowerBus OLL FIR Register for the second link. The error is harmless,
as we'll eventually setup the second link, but there's no reason to
raise that FIR bit.

The fix is simply to only enable the ODL we are using for the link.

Signed-off-by: Frederic Barrat <fbarrat at linux.vnet.ibm.com>
---
 hw/npu2-opencapi.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c
index 135accab..0eb5df5e 100644
--- a/hw/npu2-opencapi.c
+++ b/hw/npu2-opencapi.c
@@ -238,9 +238,23 @@ static void enable_odl_phy_mux(uint32_t gcid, int index)
 	/* PowerBus OLL PHY Training Config Register */
 	xscom_read(gcid, phy_config_scom, &reg);
 
-	/* Enable ODLs to use shared PHYs */
-	reg |= OBUS_IOOL_PHY_CONFIG_ODL0_ENABLED;
-	reg |= OBUS_IOOL_PHY_CONFIG_ODL1_ENABLED;
+	/*
+	 * Enable ODL to use shared PHYs
+	 *
+	 * On obus3, OTL0 is connected to ODL1 (and OTL1 to ODL0), so
+	 * even if it may look odd at first, we do want to enable ODL0
+	 * for links 2 and 5
+	 */
+	switch (index) {
+	case 2:
+	case 5:
+		reg |= OBUS_IOOL_PHY_CONFIG_ODL0_ENABLED;
+		break;
+	case 3:
+	case 4:
+		reg |= OBUS_IOOL_PHY_CONFIG_ODL1_ENABLED;
+		break;
+	}
 
 	/*
 	 * Based on the platform, we may have to activate an extra mux
-- 
2.14.1