[Skiboot] [PATCH v2] plat/qemu: add PNOR support

[Joel Stanley]

Hi Cedric,

On 12 June 2018 at 18:46, Cédric Le Goater <clg at kaod.org> wrote:
> To access the PNOR, OPAL/skiboot drives the BMC SPI controller using
> the iLPC2AHB device of the BMC SuperIO controller and accesses the
> flash contents using the LPC FW address space on which the PNOR is
> remapped.
>
> The QEMU PowerNV machine now integrates such models (SuperIO
> controller, iLPC2AHB device) and also a pseudo Aspeed SoC AHB memory
> space populated with the SPI controller registers (same model as for
> ARM). The AHB window giving access to the contents of the BMC SPI
> controller flash modules is mapped on the LPC FW address space.
>
> The change should be compatible for machine without PNOR support.
>
> Signed-off-by: Cédric Le Goater <clg at kaod.org>
> ---
>
>  The resulting machine is quite hybrid as it is mixing ARM and PPC
>  models but it is a good way to validate their exactitude and
>  completeness. We still need to work on model for the LPC bus.
>
>  Changes since v1:
>
>  - added the preload ops so that a QEMU PowerNV machine can be started
>    without a kernel and an initrd :
>
>    qemu-system-ppc64 -m 2G -machine powernv -cpu POWER8 \
>         -bios ./skiboot.lid \
>         -drive file=./palmetto.pnor,format=raw,if=mtd  \
>         -serial mon:stdio -nographic -nodefaults -snapshot

This is very cool. Thanks for doing this.

I assume I need a qemu patch to test it out?

The only nit we have is on P9 and ast2500, we don't access the SPI
controller from the host at all. We communicate through the mbox
protocol instead.

Cheers,

Joel

>
>  platforms/qemu/qemu.c | 8 ++++++++
>  platforms/qemu/qemu.c |   10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> Index: skiboot.git/platforms/qemu/qemu.c
> ===================================================================
> --- skiboot.git.orig/platforms/qemu/qemu.c
> +++ skiboot.git/platforms/qemu/qemu.c
> @@ -24,6 +24,8 @@
>  #include <bt.h>
>  #include <errorlog.h>
>  #include <ipmi.h>
> +#include <ast.h>
> +#include <platforms/astbmc/astbmc.h>
>
>  /* BT config */
>  #define BT_IO_BASE     0xe4
> @@ -78,6 +80,9 @@ static void qemu_ipmi_setenables(void)
>
>  static void qemu_init(void)
>  {
> +       /* Initialize PNOR/NVRAM */
> +       pnor_init();
> +
>         /* Setup UART console for use by Linux via OPAL API */
>         set_opal_console(&uart_opal_con);
>
> @@ -241,6 +246,9 @@ static bool qemu_probe(void)
>
>         psi_set_external_irq_policy(EXTERNAL_IRQ_POLICY_SKIBOOT);
>
> +       /* Initialize AHB accesses via AST2400 */
> +       ast_io_init();
> +
>         /* Setup UART and use it as console */
>         uart_init();
>
> @@ -254,5 +262,7 @@ DECLARE_PLATFORM(qemu) = {
>         .external_irq   = qemu_ext_irq_serirq_cpld,
>         .cec_power_down = qemu_ipmi_power_down,
>         .cec_reboot     = qemu_ipmi_reboot,
> +       .start_preload_resource = flash_start_preload_resource,
> +       .resource_loaded        = flash_resource_loaded,
>         .terminate      = ipmi_terminate,
>  };