[Skiboot] [PATCH 2/2] PM: Fixed generation of MTSPR instruction in STOP API.

[Vaidyanathan Srinivasan]

* Stewart Smith <stewart at linux.vnet.ibm.com> [2018-01-25 10:28:46]:

> From: Prem Shanker Jha <premjha2 at in.ibm.com>
> 
> STOP API generates SPR restore instruction for a given SPR.
> Commit fixes the generation of mtspr instruction by API.
> Problem will show up only when API is changed to generate
> restore instruction using a GPR other than R0.

Missing fixes.  Needed on P9 stable branches.

Acked-by: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>

> 
> Cc: stable
> CQ: SW407799
> Change-Id: I2a841a9aae417b7bcd92a323197d9c6a1f3cb149
> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49525
> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot at us.ibm.com>
> Tested-by: Jenkins Server <pfd-jenkins+hostboot at us.ibm.com>
> Tested-by: Hostboot CI <hostboot-ci+hostboot at us.ibm.com>
> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr at in.ibm.com>
> Reviewed-by: STEWART E. SMITH <stewart at linux.vnet.ibm.com>
> Dev-Ready: Gregory S. Still <stillgs at us.ibm.com>
> Reviewed-by: Gregory S. Still <stillgs at us.ibm.com>
> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49529
> Reviewed-by: Hostboot Team <hostboot at us.ibm.com>
> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot at us.ibm.com>
> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot at us.ibm.com>
> Reviewed-by: Christian R. Geddes <crgeddes at us.ibm.com>
> [stewart: cherry-picked from hostboot]
> Signed-off-by: Stewart Smith <stewart at linux.vnet.ibm.com>
> ---
>  libpore/p9_stop_api.C | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/libpore/p9_stop_api.C b/libpore/p9_stop_api.C
> index 7242c423c652..5c0f2e5e5641 100644
> --- a/libpore/p9_stop_api.C
> +++ b/libpore/p9_stop_api.C
> @@ -258,7 +258,7 @@ static uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr )
>      uint32_t mtsprInstOpcode = 0;
>      uint32_t temp = (( i_Spr & 0x03FF ) << 11);
>      mtsprInstOpcode = (uint8_t)i_Rs << 21;
> -    mtsprInstOpcode = ( temp  & 0x0000F800 ) << 5;
> +    mtsprInstOpcode |= ( temp  & 0x0000F800 ) << 5;
>      mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5;
>      mtsprInstOpcode |= MTSPR_BASE_OPCODE;
>  
> -- 
> 2.14.3
> 
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