[Skiboot] [PATCH 1/2] npu2-hw-procedures.c: Power up lanes during ntl reset

[Alistair Popple]

Newer versions of Hostboot will not power up the NVLink PHY lanes by
default. The phy_reset procedure already powers up the lanes but they also
need to be powered up in order to access the DL.

The reset_ntl procedure is called by the device driver to bring the DL out
of reset and get it into a working state. Therefore we also need to add
lane and clock power up to the reset_ntl procedure.

Signed-off-by: Alistair Popple <alistair at popple.id.au>
---
 hw/npu2-hw-procedures.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
index 1318e867..a43952d7 100644
--- a/hw/npu2-hw-procedures.c
+++ b/hw/npu2-hw-procedures.c
@@ -236,9 +236,22 @@ static bool poll_fence_status(struct npu2_dev *ndev, uint64_t val)
 static uint32_t reset_ntl(struct npu2_dev *ndev)
 {
 	uint64_t val;
+	int lane;
 
 	set_iovalid(ndev, true);
 
+	/* Power on clocks */
+	phy_write(ndev, &NPU2_PHY_RX_CLKDIST_PDWN, 0);
+	phy_write(ndev, &NPU2_PHY_RX_IREF_PDWN, 1);
+	phy_write(ndev, &NPU2_PHY_TX_CLKDIST_PDWN, 0);
+	phy_write(ndev, &NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN, 0);
+
+	FOR_EACH_LANE(ndev, lane) {
+		phy_write_lane(ndev, &NPU2_PHY_RX_LANE_ANA_PDWN, lane, 0);
+		phy_write_lane(ndev, &NPU2_PHY_RX_LANE_DIG_PDWN, lane, 0);
+		phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
+	}
+
 	/* Write PRI */
 	val = SETFIELD(PPC_BITMASK(0,1), 0ull, obus_brick_index(ndev));
 	npu2_write_mask(ndev->npu, NPU2_NTL_PRI_CFG(ndev), val, -1ULL);
-- 
2.11.0