[Skiboot] [PATCH] ATTN: Enable flush instruction cache bit in HID register
Vasant Hegde
hegdevasant at linux.vnet.ibm.com
Mon Jan 15 20:23:51 AEDT 2018
In P9, we have to enable "flush the instruction cache" bit along with
"attn instruction support" bit to trigger attention.
Signed-off-by: Vasant Hegde <hegdevasant at linux.vnet.ibm.com>
---
Stewart,
"flush the instruction cache" bit is disabled by default. Hence I
think we don't have any side effect.
-Vasant
include/processor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/processor.h b/include/processor.h
index 69c5d4a4e..925cc7cd8 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -181,7 +181,7 @@
#define SPR_HID0_POWER8_HILE PPC_BIT(19)
#define SPR_HID0_POWER9_HILE PPC_BIT(4)
#define SPR_HID0_POWER8_ENABLE_ATTN PPC_BIT(31)
-#define SPR_HID0_POWER9_ENABLE_ATTN PPC_BIT(3)
+#define SPR_HID0_POWER9_ENABLE_ATTN (PPC_BIT(2) | PPC_BIT(3))
#define SPR_HID0_POWER9_RADIX PPC_BIT(8)
/* PVR bits */
--
2.14.3
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