[Skiboot] [PATCH 5/9] npu2-opencapi: Configure NPU for OpenCAPI

[Andrew Donnellan]

On 12/01/18 00:31, Frederic Barrat wrote:
>> +static void enable_sm_allocation(uint32_t gcid, uint32_t scom_base, 
>> int index)
>> +{
>> +    uint64_t reg;
>> +    int stack = index_to_stack(index);
>> +
>> +    prlog(PR_DEBUG, "OCAPI: %s: Enable State Machine Allocation\n", 
>> __func__);
>> +    /* Step 8 - Enable state-machine allocation */
>> +    /* Low-Water Marks Registers - Enable state machine allocation */
>> +    for (uint64_t block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; 
>> block++) {
> 
> The 'block' declaration is following an usual coding style.

ACK

> 
>> +        reg = npu2_scom_read(gcid, scom_base,
>> +                     NPU2_REG_OFFSET(stack, block,
>> +                             NPU2_LOW_WATER_MARKS),
>> +                     NPU2_MISC_DA_LEN_8B);
>> +        reg |= NPU2_LOW_WATER_MARKS_ENABLE_MACHINE_ALLOC;
>> +        npu2_scom_write(gcid, scom_base,
>> +                NPU2_REG_OFFSET(stack, block,
>> +                        NPU2_LOW_WATER_MARKS),
>> +                NPU2_MISC_DA_LEN_8B, reg);
>> +    }
>> +}
>> +
>> +static void enable_pb_snooping(uint32_t gcid, uint32_t scom_base, int 
>> index)
>> +{
>> +    uint64_t reg;
>> +    int stack = index_to_stack(index);
>> +
>> +    prlog(PR_DEBUG, "OCAPI: %s: Enable PowerBus snooping\n", __func__);
>> +    /* Step 9 - Enable PowerBus snooping */
>> +    /* CQ_SM Misc Config Register #0 - Enable PowerBus snooping */
>> +    for (uint64_t block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; 
>> block++) {
> 
> Same here.

ACK

> 
>> +        reg = npu2_scom_read(gcid, scom_base,
>> +                     NPU2_REG_OFFSET(stack, block,
>> +                             NPU2_CQ_SM_MISC_CFG0),
>> +                     NPU2_MISC_DA_LEN_8B);
>> +        reg |= NPU2_CQ_SM_MISC_CFG0_CONFIG_ENABLE_PBUS;
>> +        npu2_scom_write(gcid, scom_base,
>> +                NPU2_REG_OFFSET(stack, block,
>> +                        NPU2_CQ_SM_MISC_CFG0),
>> +                NPU2_MISC_DA_LEN_8B, reg);
>> +    }
>> +}
>> +

...

>> +static int setup_irq(struct npu2 *p)
>> +{
>> +    uint64_t reg, mmio_addr;
>> +    uint32_t base;
>> +
>> +    base = xive_alloc_ipi_irqs(p->chip_id, NPU_IRQ_LEVELS, 64);
> 
> Mea culpa: we should use a macro instead of "64". That's likely 
> temporary anyway, as it should be merged down the road with nvlink 
> (Alistair's has just sent a related patch).
> 

Will take a look


-- 
Andrew Donnellan              OzLabs, ADL Canberra
andrew.donnellan at au1.ibm.com  IBM Australia Limited