[Skiboot] [PATCH 2/3] npu2: hw-procedures: Manipulate IOVALID during training

[Alistair Popple]

I guess this is ok, although we have zero documentation to confirm what any of
this does other than it's just magic that apparently makes things work better.

Acked-By: Alistair Popple <alistair at popple.id.au>

On Monday, 27 November 2017 6:10:53 PM AEDT Reza Arbab wrote:
> Ensure that the IOVALID bit for this brick is raised at the start of
> link training, in the reset_ntl procedure.
> 
> Then, to protect us from a glitch when the PHY clock turns off or gets
> chopped, lower IOVALID for the duration of the phy_reset and
> phy_rx_dccal procedures.
> 
> Signed-off-by: Reza Arbab <arbab at linux.vnet.ibm.com>
> ---
>  hw/npu2-hw-procedures.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
> index 4c9d843..879ffe7 100644
> --- a/hw/npu2-hw-procedures.c
> +++ b/hw/npu2-hw-procedures.c
> @@ -203,6 +203,20 @@ static int obus_brick_index(struct npu2_dev *ndev)
>  	return index;
>  }
>  
> +static void set_iovalid(struct npu2_dev *ndev, bool raise)
> +{
> +	uint64_t addr, val, mask;
> +	int rc;
> +
> +	addr = (ndev->pl_xscom_base & 0x3F000000) | 0x9;
> +	mask = PPC_BIT(6 + obus_brick_index(ndev));
> +	val = raise ? mask : 0;
> +
> +	rc = xscom_write_mask(ndev->npu->chip_id, addr, val, mask);
> +	if (rc)
> +		NPU2DEVERR(ndev, "error %d writing scom 0x%llx\n", rc, addr);
> +}
> +
>  static bool poll_fence_status(struct npu2_dev *ndev, uint64_t val)
>  {
>  	uint64_t fs;
> @@ -223,6 +237,8 @@ static uint32_t reset_ntl(struct npu2_dev *ndev)
>  {
>  	uint64_t val;
>  
> +	set_iovalid(ndev, true);
> +
>  	/* Write PRI */
>  	val = SETFIELD(PPC_BITMASK(0,1), 0ull, obus_brick_index(ndev));
>  	npu2_write_mask(ndev->npu, NPU2_NTL_PRI_CFG(ndev), val, -1ULL);
> @@ -304,6 +320,8 @@ static uint32_t phy_reset(struct npu2_dev *ndev)
>  {
>  	int lane;
>  
> +	set_iovalid(ndev, false);
> +
>  	/* Power on clocks */
>  	phy_write(ndev, &NPU2_PHY_RX_CLKDIST_PDWN, 0);
>  	phy_write(ndev, &NPU2_PHY_RX_IREF_PDWN, 1);
> @@ -360,6 +378,8 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev)
>  		phy_write_lane(ndev, &NPU2_PHY_RX_E_INTEG_COARSE_GAIN, lane, 11);
>  	}
>  
> +	set_iovalid(ndev, true);
> +
>  	return PROCEDURE_COMPLETE;
>  }
>  DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete);
> @@ -572,6 +592,8 @@ static uint32_t phy_rx_dccal(struct npu2_dev *ndev)
>  {
>  	int lane;
>  
> +	set_iovalid(ndev, false);
> +
>  	FOR_EACH_LANE(ndev, lane)
>  		phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 1);
>  
> @@ -598,6 +620,8 @@ static uint32_t phy_rx_dccal_complete(struct npu2_dev *ndev)
>  		phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 0);
>  	}
>  
> +	set_iovalid(ndev, true);
> +
>  	return PROCEDURE_NEXT;
>  }
>  
>