[Skiboot] [PATCH] power-mgmt : occ : Add 'freq-domain-indicator' DT property

[Abhishek Goel]

Add a new device-tree property freq-domain-indicator to define group of
CPUs which would share same frequency. This property has been added under
power-mgmt node.

It is a bitmask which will have different value depending upon the
generation of the processor. Bitwise AND is taken between this bitmask
value and PIR of cpu. All the CPUs lying in the same frequency domain will
have same result for AND.

For example, for POWER8 0xFFF8 indicates core wide frequency domain.
Taking AND with the PIR of CPUs will yield us a frequency domain which is
core wide distribution as last 3 bits have been masked which represent the
threads.

For POWER9, 0xFFF0 indicates quad wide frequency domain. Taking AND with
the PIR of CPUs will yield us frequency domain which is quad wise
distribution as last 4 bits have been masked which represent the cores.

Signed-off-by: Abhishek Goel <huntbag at linux.vnet.ibm.com>
---
 doc/device-tree/ibm,opal/power-mgt/occ.rst | 11 +++++++++++
 hw/occ.c                                   | 16 ++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/doc/device-tree/ibm,opal/power-mgt/occ.rst b/doc/device-tree/ibm,opal/power-mgt/occ.rst
index d13a62b..17c866f 100644
--- a/doc/device-tree/ibm,opal/power-mgt/occ.rst
+++ b/doc/device-tree/ibm,opal/power-mgt/occ.rst
@@ -37,3 +37,14 @@ ibm,pstate-vcss ibm,pstate-vdds
 These properties list a voltage-identifier of each of the pstates listed in
 ibm,pstate-ids for the Vcs and Vdd values used for that pstate in that chip.
 Each VID is a single byte.
+
+ibm,opal/power-mgt/ibm,freq-domain-indicator
+--------------------------------------------
+
+This property is a bitmask which will have different value depending upon
+the generation of the processor. Frequency domain would indicate group of
+CPUs which would share same frequency. Bitwise AND is taken between this
+bitmask value and PIR of cpu. All the CPUs lying in the same frequency
+domain will have same result for AND. Thus frequency management can be
+done based on frequency-domain. A frequency domain may be a core or a
+quad, etc depending upon the generation of the processor.
diff --git a/hw/occ.c b/hw/occ.c
index 78c6a6a..7773c97 100644
--- a/hw/occ.c
+++ b/hw/occ.c
@@ -47,6 +47,9 @@
 #define MAX_OPAL_CMD_DATA_LENGTH	4090
 #define MAX_OCC_RSP_DATA_LENGTH		8698
 
+#define P8_PIR_CORE_MASK		0xFFF8
+#define P9_PIR_QUAD_MASK		0xFFF0
+
 /**
  * OCC-OPAL Shared Memory Region
  *
@@ -488,6 +491,7 @@ static bool add_cpu_pstate_properties(int *pstate_nom)
 	u8 nr_pstates;
 	bool ultra_turbo_supported;
 	int i;
+	u32 freq_domain_mask = 0;
 
 	prlog(PR_DEBUG, "OCC: CPU pstate state device tree init\n");
 
@@ -658,6 +662,15 @@ static bool add_cpu_pstate_properties(int *pstate_nom)
 		return false;
 	}
 
+	if (proc_gen == proc_gen_p8)
+		freq_domain_mask = P8_PIR_CORE_MASK;
+	else if (proc_gen == proc_gen_p9)
+		freq_domain_mask = P9_PIR_QUAD_MASK;
+	else
+		prerror("OCC: freq-domain-indicator :
+					 Processor is not supported\n");
+
+
 	/* Add the device-tree entries */
 	dt_add_property(power_mgt, "ibm,pstate-ids", dt_id,
 			nr_pstates * sizeof(u32));
@@ -666,6 +679,9 @@ static bool add_cpu_pstate_properties(int *pstate_nom)
 	dt_add_property_cells(power_mgt, "ibm,pstate-min", pmin);
 	dt_add_property_cells(power_mgt, "ibm,pstate-nominal", pnom);
 	dt_add_property_cells(power_mgt, "ibm,pstate-max", pmax);
+	dt_add_property_cells(power_mgt, "ibm,freq-domain-indicator",
+							 freq_domain_mask);
+
 
 	free(dt_freq);
 	free(dt_id);
-- 
2.9.3