[Skiboot] [PATCH 2/3] npu2: hw-procedures: Add phy_rx_clock_sel()

[alistair at popple.id.au]

Normally we wouldn't touch DL registers from Skiboot, but this is specific
to the IBM implementation of the DL so in this case it makes sense to put
it here.

Reviewed-By: Alistair Popple <alistair at popple.id.au>

> Change the RX clk mux control to be done by software instead of HW. This
> avoids glitches caused by changing the mux setting.
>
> Signed-off-by: Reza Arbab <arbab at linux.vnet.ibm.com>
> ---
>  hw/npu2-hw-procedures.c | 20 +++++++++++++++++++-
>  include/npu2-regs.h     |  1 +
>  2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c
> index 7a5d188..c24489f 100644
> --- a/hw/npu2-hw-procedures.c
> +++ b/hw/npu2-hw-procedures.c
> @@ -561,6 +561,23 @@ static uint32_t phy_rx_dccal_complete(struct npu2_dev
> *ndev)
>  	return PROCEDURE_NEXT;
>  }
>
> +static uint32_t phy_rx_clock_sel(struct npu2_dev *ndev)
> +{
> +	/*
> +	 * Change the RX clk mux control to be done by software instead of HW.
> This
> +	 * avoids glitches caused by changing the mux setting.
> +	 *
> +	 * Work around a known DL bug by doing these writes twice.
> +	 */
> +	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000003,
> 0x80000003);
> +	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000003,
> 0x80000003);
> +
> +	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000001,
> 0x80000003);
> +	npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev), 0x80000001,
> 0x80000003);
> +
> +	return PROCEDURE_NEXT;
> +}
> +
>  /* Procedure 1.2.5 - IO PHY Tx FIFO Init */
>  static uint32_t phy_tx_fifo_init(struct npu2_dev *ndev)
>  {
> @@ -577,7 +594,8 @@ static uint32_t phy_tx_fifo_init(struct npu2_dev
> *ndev)
>
>  /* We group TX FIFO init in here mainly because that's what was done
>   * on NVLink1 */
> -DEFINE_PROCEDURE(phy_rx_dccal, phy_rx_dccal_complete, phy_tx_fifo_init);
> +DEFINE_PROCEDURE(phy_rx_dccal, phy_rx_dccal_complete, phy_rx_clock_sel,
> +		 phy_tx_fifo_init);
>
>  /* Procedure 1.2.7 - I/O PHY Upstream Link Training */
>  static uint32_t phy_rx_training(struct npu2_dev *ndev)
> diff --git a/include/npu2-regs.h b/include/npu2-regs.h
> index 759404c..d35cc44 100644
> --- a/include/npu2-regs.h
> +++ b/include/npu2-regs.h
> @@ -275,6 +275,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg,
> uint64_t val, uint64_t mask);
>  #define NPU2_NTL_CQ_FENCE_STATUS(ndev)		NPU2_NTLU_REG_OFFSET(ndev, 0x500)
>  #define NPU2_NTL_DL_CONTROL(ndev)		NPU2_DL_REG_OFFSET(ndev, 0xFFF4)
>  #define NPU2_NTL_DL_CONFIG(ndev)		NPU2_DL_REG_OFFSET(ndev, 0xFFF8)
> +#define NPU2_NTL_DL_CLK_CTRL(ndev)		NPU2_DL_REG_OFFSET(ndev, 0x001C)
>
>  /* Misc block registers. Unlike the SM/CTL/DAT/NTL registers above
>   * there is only a single instance of each of these in the NPU so we
> --
> 1.8.3.1
>
>